Those attempting to predict the next camera-to-computer interface standard have been thrown a number of curve balls lately. At the 2009 International Robots, Vision & Motion Control Show in Rosemont, IL, for example, two proposals to extend the bandwidth of the Camera Link interface were presented to the standards committee of the Automated Imaging Association (AIA) (see “Future Camera Link standards emerge,”Vision Systems Design, August 2009).
The first, CoaXPress, proposed by Adimec (Eindhoven, the Netherlands; www.adimec.com) is based on a high-speed line driver and equalizer chipset from Eqcologic (Brussels, Belgium; www.eqcologic.com) and allows image data to be transferred over 50 m of coaxial cable at a data rate of 6.25 Gbits/s. For higher speeds, more cables can be used in parallel.
The second approach known as high-speed link (HSLINK), proposed by DALSA (Waterloo, ON, Canada; www.dalsa.com) specifies each twisted pair in the cable runs at 3.125 Gbits/s, with options for one pair, four pairs, and 20 pairs that would support up to 62.5 Gbits/s using a 12x InfiniBand cable. While camera products and frame grabbers based on the CoaXPress standard from Adimec and Active Silicon (Iver, UK; www.activesilicon.com), respectively, were announced at the November VISION 2009 show in Stuttgart, Germany, the HSLINK proposal has yet to see any product adoption.
Because interfaces such as Camera Link, CoaXPress, and InfiniBand all offer point-to-point bidirectional serial links, they are by nature more deterministic than bus-based standards such as USB- or frame-based protocols such as Gigabit Ethernet. Despite this, low-cost consumer interfaces such as USB 3.0 will gain ground in PC-based systems that do not necessarily require high-speed deterministic response.
After Intel initially demonstrated the USB 3.0 or SuperSpeed interface more than two years ago, the 4.8-Gbit/s interface and products developed using it were recently unveiled at the September 2009 Intel Developer Forum (San Francisco, CA, USA).
To increase the bandwidth of the USB 3.0 interface, the SuperSpeed standard adds two extra differential pairs that are operated in full duplex mode. To remain backwards compatible, the SuperSpeed standard retains the original differential pair used to transmit data in the USB 2.0 standard.
When implementing the USB interface, system developers have a number of choices. These include using dedicated host controller interfaces, USB 3.0 transceivers, and PCI Express controllers, whether to implement some or all of this functionality in an ASIC, or to integrate single ICs that incorporate all of these functions.
Those wishing to prototype systems rapidly could, for example, opt for the FL1000 single-chip solution from Fresco Logic (Beaverton, OR, USA; www.frescologic.com). Backwards compatible with USB 1.1 and 2.0, the 100-pin device supports the USB 3.0 Rev 1.0 standard and implements a host PCI Express interface, USB 3.0 transceiver, a USB 3.0 eXtended Host Controller Interface (xHCI), and a PCI Express controller and transceiver. The company is also offering an FL1000-enabled add-in card for PCI Express systems.
Leveraging this technology, Point Grey Research (Richmond, BC, Canada; www.ptgrey.com) has already demonstrated the benefits of SuperSpeed USB by streaming uncompressed 1080p60 video from a Point Grey camera to the USB 3.0 host controller from Fresco Logic running in an P7P55D motherboard from Asus (Taipei, Taiwan; www.asus.com). The prototype camera uses a 3-Mpixel IMX036 CMOS image sensor from Sony (Tokyo, Japan; www.sony.com) to output uncompressed 1920 × 1080-pixel images at 60 frames/s (see figure). Point Grey’s software driver provides low-level control of the camera via the USB 3.0 bus.
While the USB SuperSpeed interface represents a direct challenge to other bus-based standards such as FireWire, other emerging technologies from Intel promise to further increase the bandwidth of consumer interfaces. At the Intel Developer Forum, for example, Intel demonstrated what it is calling Light Peak, an integrated controller and optical module that uses miniature lasers and photodetectors to deliver 10 Gbits/s over an optical fiber.
Although details of the device have yet to be made available, the company has said that the interface is expected to be an order of magnitude less expensive than current 10-Gbit/s transceivers and controllers. Intel expects this technology to be scalable to 100 Gbits/s over the next decade and plans to offer the controller chip to developers next year.
