Targeting imaging, wireless, and broadband data communications, Texas Instruments (TI; Houston, TX) has extended the architecture of its C60 family by introducing the C64x, fixed-point VLIW digital-signal processor (DSP). Initial devices are sampling in the 600-800-MHz range, giving maximum performance levels of 4800-6400 MIPS. To attain this level of performance, the company has added new instructions and extended the parallelism of the architecture.
On TI's C6000 devices, there are two general-purpose register files (A and B) in the data paths. The C62x/C67x parts contains sixteen 32-bit registers. In the C64x, there are thirty-two 32-bit registers per data path.
In every C6000 series part, data paths are divided into two groups of four (see diagram). Besides performing all the C62x instructions, the C64x also contains 8- and 16-bit extensions to the instruction set that include quad 8 x 8 multiply operations, dual 16 x 16 multiply operations, and dual 16 x 16 multiply with add/subtract operations. Although TI has modified the hardware of the C62x/C67x to attain these performance increases, the C64x is object-code compatible with the C62x. To support the new part, TI has released Version 4.0 of its C6000 Compiler that supports the C62x/C67x and C64x. According to the company, compiler performance will be enhanced for the C64x architecture in subsequent releases.
In the design of Texas Instruments' C64x series VLIW processor, the architecture of the C62x/C67x has been augmented with the addition of new hardware elements. In the C64x, data paths are still divided into two groups of four and the part remains code-compatible with other members of the C6x family.
To jump-start the development of image-processing and video applications, TI has designed an imaging developers kit, based on the C6711 32-bit floating-point DSP. Included in the kit are a processor board, an add-on board for digitizing NTSC or PAL video data, a video camera, video and imaging demonstration programs, and the company's Code Composer Studio IDE.
Despite the large MIPS numbers touted by TI, most applications will never attain this maximum performance. Says Chris Bore, vice president of sales, marketing, and training at Momentum Data Systems (Woking, Surrey, England), "Although TI shows the C60 block diagram as having four arithmetic units in each data path, the fourth unit is used for address generation calculation." Although the C60 can choose to use the address-generation unit for general-purpose calculations if it is not calculating addresses, for most classic DSP operations address generation would be required. Thus, this unit would not be available for general-purpose use.
Says Bore, "Although TI may rate the C60 as a 1600-MIPS device on the basis that it runs at 200 MHz and has two data paths, each with four execution units, there may only be three execution units being used per data path. Thus, the maximum achievable throughput is 200 MHz x 2 x 3, or 1200 MIPS. "This illustrates a problem in evaluating DSPs," says Bore. "It is very hard to compare like with like—not least, because all manufacturers present their designs in such a way that they show their best performance. One cannot rely on MIPS, MOPS, or MFLOPs ratings but must try to understand the features of each candidate processor and how they differ from each other.
Prior to placing flux or spheres on the substrate of the area array package ball-grid array (BGA), fiducials are aligned so that BGAs or chip-scale packages can be aligned with the ball-placement mechanism of the system.
Doug Adkins takes a closeup view of the minirobots he and Ed Heller are developing at Sandia National Laboratories. At 0.25 in.3 and weighing less than an ounce, they are possibly the smallest autonomous untethered robots ever created.
