High-performance vision systems must handle large amounts of data in close to real time. Features of such systems include multiple processors, large memories, and high-speed I/O. Applications range from automated printing inspection, real-time medical imaging, and synthetic aperture radar, to automatic target recognition. To handle these processor and I/O trade-offs, vendors are beefing up VME with 64-bit extensions that double the data rate to 160 Mbyte/s, while at the same time adding high-spe

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By John Haystead, Contributing Editor

High-performance vision systems must handle large amounts of data in close to real time. Features of such systems include multiple processors, large memories, and high-speed I/O. Applications range from automated printing inspection, real-time medical imaging, and synthetic aperture radar, to automatic target recognition. To handle these processor and I/O trade-offs, vendors are beefing up VME with 64-bit extensions that double the data rate to 160 Mbyte/s, while at the same time adding high-speed dedicated interconnect schemes.

According to Rich Jaenicke, director of marketing for Sky Computers Inc. (Chelmsford, MA), a common problem in vision-system design is that data-flow architectures are ignored. "Processor choice must be weighed against I/O performance. Developers should first determine their I/O bandwidth requirements, and because communication backbones do not develop at the same speed as processors, systems should satisfy different levels of requirements and provide sufficient bandwidth to handle future processors."

To accommodate the high-speed I/O required in image processing, Sky uses the VME`s P2 connector for it`s SkyChannel packet bus (see Fig. 1). Capable of a 320-Mbyte/s throughput, the bus can be used in either a single channel or point-to-point configuration.

Mercury Computer Systems (Chelmsford, MA) also emphasizes its system-level approach to VME-based image-processing design. Says Gary Olin, manager of strategic marketing, "Although signal-processing systems may approach or exceed the communication-bandwidth requirements of imaging systems, digital signal processors (DSPs) are often not suited for imaging. "Image-processing algorithms such as feature analysis and extraction tasks are better handled by RISC processors," he says, "although some designers use DSPs for front-end data filtering and transformation functions. Mercury provides both capabilities in the same system."

Like Sky, Mercury also offers a means of transferring data at high speed. Using a crossbar switch, Mercury`s RACE series of SHARC DSP boards can be linked at speeds up to 160 Mbyte/s (see Fig. 2).

Development tools

While processor performance specs are important, vision-system designers must ensure that algorithms will run efficiently. Sky`s Jaenicke points out that "image-processing developers tend to rely more on compilers than do DSP designers who perform more hand coding." Because ease of use has an impact on time to market, designers, should favor high-level architectures that do not require extensive development time.

Mercury`s Olin agrees. "There`s a tremendous push for better software tools, mostly for application development." As system environments are more complex, scientific-algorithm library support is important. To program efficiently in assembly language on a particular processor often takes too long.

"Network multicomputing is the next frontier for high-performance systems," claims Bernard Pelon, marketing director of CSPI (Billerica, MA). That`s why, rather than build its own proprietary high-speed interconnect, CSPI has chosen to collaborate with Myricom (Arcadia, CA) to allow systems integrators to transfer data at 1.28 Gbyte/s using the Myrinet standard. CSPI offers the interface as an optional PMC card to the company`s MAP-1310 series of SHARC-based image processors (see Fig. 3).

Despite its data-capacity limitations, the VME will continue to be the architecture of choice for high-end image-processing applications because of the architecture`s flexibility. With the P2 connector, VME can host alternative I/O technologies such as PCI very efficiently. Using interlink schemes, it can overcome bandwidth and bottleneck problems to other processors on the board or to nodes on another board. Steve Curtin, marketing manager for Ariel Corp. (Cranbury, NJ), believes the VME bus will continue to be important. "Although PCI is catching on, there`s an existing investment in deployed VME systems," he says.

Unlike Mercury and Sky, Ariel`s latest C40 Hydra use the I/O of the processors to transfer data (see Fig. 4). Systems developers can transfer data using communication ports on the C40 that allow 20-Mbyte/s data transfers. Alternatively, two 100-Mbyte/s on-chip global buses can be used.

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FIGURE 1. Sky Computer`s SKYchannel is a 64-bit, 40-MHz packet bus that provides data throughput of 320 Mbyte/s. SKYchannel can be implemented as either a single-channel bus or in a point-to-point configuration using a crossbar-based backplane to increase I/O bandwidth to 1600 Mbyte/s. As a single-channel bus, a 72-bit-wide signal path carries data at 40 MHz. Board-to-board transfers are handled over the VME P2 connector. Sky boards use the VME64 parallel I/O for control and communication to other VME boards.

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FIGURE 2. MercuryComputer System`s RACE series boards can be configured with up to 48 SHARC processors on a single 9U VME or four 6U boards to provide 5 GFLOPS. To overcome the limitations of conventional SHARC link-port designs, Mercury`s RACEway (ANSI/VITA 5-1994) multinode switching fabric provides a scalable network of point-to-point crossbar switches, each running at 160 Mbyte/s. At present, the RACEway interlink is implemented with six-port crossbar switches.

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FIGURE 3. CSPI`s MAP-1310 boards are based on a VME form factor, PowerPC 603, and a VME64 interface. PMC module cards host four or eight SHARC ADSP-21060 processors that connect to the VME motherboard via a 32-bit PCI/PMC mezzanine slot or via the VME P2 connector. Optionally, systems developers can add a PMC-based Myrinet interface to allow data transfer at up to 1.28 Gbyte/s.

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FIGURE 4. Ariel`s Hydra II VME boards host four 60-MHz C40s with up to 32 Mbyte of memory and deliver 240 MFLOPS. Four of the six 20-Mbyte/s communication ports on each C40 are available as external ports. The remaining two ports are used for inter-processor communications. Global memory buses (100 Mbyte/s) on two of the C40s are also available as external ports and provide an external 25-Mbyte/s VSB interface via the VME P2 connector.

Compact PCI challenges VME

For the foreseeable future, VME will be the platform for high-performance image-processing applications. Indications are, however, that VME may lose ground to PCI-based systems. "The broad markets for machine vision and imaging are in the PCI world," says Ariel Corp.`s Steve Curtin. Although Ariel considered implementing a VME version of its C80-based Griffin PCI board in VME, customer demand was not high. "Most image-processing systems are PC-based, with developers coupling inexpensive PCI frame grabbers and cameras to off-the-shelf operating systems--a trend that will be fueled by the adoption of compact PCI.

Rich Jaenicke of Sky Computers Inc. (Chelmsford, MA) agrees. While there is a large business in industrial imaging, there are fewer high-end applications. Jaenicke sees a move to PCI or discrete systems except for high-performance applications such as machine vision. "Cost issues are a huge factor. As soon as there is enough processing power and speed to solve an application, boards become smaller, faster, and cheaper. As this happens, developers may move away from VME to PCI."

Image processing brings the cosmos closer

The Hubble Space Telescope is testimony to the difficulties the Earth`s atmosphere poses to ground-based astronomical observation. But new image-processing and correction mechanisms are dramatically improving the resolution of ground-based telescopes.

At the Max Planck Institute of Astronomy (Heidelburg, Germany), such a system is improving the resolution of a 3 1/2-mm telescope. Built by Adaptive Optics Associates (AOA; Cambridge, MA), the system corrects for atmospheric conditions, increasing the system`s limited 5-arc sec resolution.

AOA developed a camera with EG&G Reticon (Sunnyvale, CA) that provides 128 outputs that must be digitized simultaneously. "Processing power was never the challenge, but I/O was," says Theresa Bruno, business area manager for AOA. "The processor must accommodate multiple data streams at 100 ms and process 128-bit words in parallel, she says.

To accomplish this, AOA used five Hydra II boards from Ariel Corp. (Cranbury, NJ) with four C40s on each. AOA chose the Ariel board because the communication ports of all the digital signal processors (DSPs) were readily available. And, because the system required large volumes of data to be handled by multiple processors, communication ports were needed to transfer data from one processor to the next.

To control the telescope, the institute used EPICS (an academically developed instrument control language) for focusing and pointing. Run under VxWorks from Wind River Systems (Alameda, CA), the VME-based system was hosted by a 68060 VME board. Software for Ariel`s DSP boards was developed on Sun SPARC workstations, with SPARC 20 workstations running the client-server software that links the operator interface via Ethernet to the 68060 board.

Kahalas says the Texas Instruments` debugging tools were adequate to compile and meet the run-time requirements for the application without the need for custom assembly code. "Today less custom design and development of cameras, ASICs, and digital signal processors is required because off-the-shelf technology can be used," says Stacey Kahalas, a software engineer on the project. Nevertheless, "it`s still often difficult to find a board that has everything we need."

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