Analog ASIC speeds image-filtering operations

In a convolution process, partial filtering requires computing the neighborhood average of the intensities of pixels at every point in an image. To optimize image-processing systems for performing this function, vendors of digital image-processing hardware use multiplier-accumulators that can perform video image filtering at high frame rates.

Jun 1st, 1998

Analog ASIC speeds image-filtering operations

In a convolution process, partial filtering requires computing the neighborhood average of the intensities of pixels at every point in an image. To optimize image-processing systems for performing this function, vendors of digital image-processing hardware use multiplier-accumulators that can perform video image filtering at high frame rates.

However, when images are large or bandpass image processing must be performed, several convolution operations must be performed. Consequently, even fast hardware-pipelined processing might not be sufficient to accommodate frame-rate imaging.

"In applications such as target tracking," says Jon S. McElvain a materials scientist with UNIAX (Santa Barbara, CA; mack@uniax. com), "small low-power devices are needed that can rapidly process 1024 ¥ 1024-pixel or larger images."

Consequently, UNIAX has teamed up with the Raytheon Infrared Center of Excellence (RIRCOE; Santa Barbara, CA) and the US Naval Research Laboratory, with funding from the Ballistic Missile Defense Organization and the Defense Advanced Research Projects Agency, to develop a thin-film analog image processor (TAIP) capable of 60-Hz-frame-rate imaging. The initial design, to be completed in August, is not an image sensor, but an array of transistors interconnected with a conducting polymer film.

In operation, analog image data are initially multiplexed into the array from a standard detector array. Then, image processing is performed, and data are demultiplexed out of the chip. According to McElvain, the proto type processor is expected to have an image-format size of 320 ¥ 240 pixels and will operate at 60 Hz.

"To remove image noise, the 30-mW IC can perform low-pass spatial filtering by averaging neighborhood pixels in the image," says McElvain. In the TAIP, this averaging is computed in analog fashion by combining the analog pixel values through the conducting polymer film at frame rates. In similar fashion, high-pass spatial filtering can sharpen or increase the contrast in images, a task accomplished by thresholding the analog voltage of each pixel in the TAIP.

"Because the TAIP can be operated as either a high-pass or a low-pass filter," says McElvain, "operating two devices in series results in a bandpass filter." Combining multiple TAIP arrays results in a system capable of versatile, high-speed image analysis that allows spatial-frequency filtering to be performed in an analog fashion. According to McElvain, future developments will include both wafer-scale integration and interconnecting flip-chip hybrid packages. These developments are expected to result in systems with greater processing power than the 100 GFLOP/s currently available with today`s digital-signal processing boards, he says.

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