FPGAs increase image-processing throughput

To increase the speed of image-processing algorithms, systems developers often need to use field-programmable-gate-array (FPGA) based add-in boards.

Jan 1st, 2004
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To increase the speed of image-processing algorithms, systems developers often need to use field-programmable-gate-array (FPGA).based add-in boards. Because of the throughput of such FPGA designs, they are often matched with high-performance image digitizers and I/O buses. One board, the Tsunami FPGA processor family from SBS Technologies (Albuquerque, NM, USA; www.sbs.com), can support a Camera Link interface and up to five EP1S25 FPGAs from Altera (San Jose, CA, USA; www.altera.com) on a 64-bit/66-MHz bus.

In the past, programming such boards has not been for the faint of heart, and it still represents a challenge. "Because the board is targeted at very-high-performance image-processing applications," says Brian Tithecott, director of sales and marketing, "it requires the programmer to be familiar with VHDL coding and intellectual-property (IP) blocks already written in VHDL."

Using the Altera Quartus compiler, VHDL can be developed for the board or built as block-level IP functions using Altera's system-on-a-programmable-chip builder. These tools are used in conjunction with the SBS Technologies Imaging Tool Kit (ITK) and the Altera Nios-configurable soft-core processor and an internal Avalon FPGA bus. In operation, the chip builder assembles image-processing functions into high-level image-processing blocks that are then linked together using the ITK for prototyping an application.

SBS Technologies Imaging Tool Kit for its Camera Link-based Tsunami machine-vision/image-processing board can be programmed by dropping IP modules in a pipelined fashion into on-board FPGAs. The company is also evaluating C-to-FPGA-based solutions.
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According to Tithecott, SBS Technologies is also exploring other ways the board can be programmed. One method uses the Platform Developer package from Celoxia (Abingdon, UK; www.celoxica.com) designed for system-level designers that wish to do evaluations using C-based programming in conjunction with FPGAs. Incorporating Celoxia's DK Design Suite base package with its Handel-C simulation environment and C-based synthesis, the software allows designers to develop functions in C-based design languages and implement them in FPGAs. This includes system codesign, coverification capabilities, C-to-RTL, and direct C-to-FPGA synthesis. "SBS is analyzing the product now and expects to offer a design around the technology very soon," says Tithecott.

"We are currently looking at a number of applications and how effectively these translate from C code to an FPGA implementation," he says. "Even if such code is only half as efficient as custom FPGA-tailored VHDL code, this will still translate into a speed-up greater than five times that of general-purpose CPU designs."

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