FRAMOS IP core and evaluation board connects Sony SLVS-EC interface with Xilinx FPGAs
FRAMOS has announced the availability of the SLVS-EC RX IP Core, which is designed to connect Sony’s new high-speed scalable low-voltage signaling embedded clock (SLVS-EC) interface with Xilinx FGPAs, which FRAMOS hopes will provide the technological basis for future camera developments and embedded vision devices.
FRAMOShas announced the availability of the SLVS-EC RX IP Core, which is designed to connect Sony’s new high-speed scalable low-voltage signaling embeddedclock (SLVS-EC) interface with Xilinx FGPAs, which FRAMOS hopes will provide the technological basis for future camera developments and embedded vision devices.
Introduced with the third generation of Pregius CMOS image sensors, Sony’s SLVS-EC interfaceoffers up to 8 lanes providing 2.3 Gbps each, for three to four times higher bandwidths, higher resolutions or a simplified system design compared to SubLVDS, according to FRAMOS. Recent sensors featuring the SLVS-EC interface include the IMX420 and IMX428. Both Pregius CMOS image sensors are 7 MPixel, diagonal 17.6 mm sensors with a 4.5 µm pixel size. The IMX420 achieves a frame rate of 134.5 fps at 12-bit depth, while the IMX428 achieves a frame rate of 51.4 fps at 12-bit depth. The IMX420 has a scalable bit depth of 8, 10, and 12 bits, and can be programmed for multiple regions of interest, while the IMX428 sensor is available only in a 12-bit model.
FRAMOS’ RX IP core reduces overhead and complexity implementing a Sony image sensor with SLVS-EC, according to the company. As on-chip function block connecting the customer's FPGA logic with the image sensor's data stream, the IP Core receives the interface data, manages the byte-to-pixel conversion for various lane configurations, according to FRAMOS. The FRAMOS software will support SLVS-EC v1.2 with 1, 2, 4, or 8 lanes configurable by the user and delivers pixels formats from 8 to 14-bit of raw data.
Simon Che'Rose, Head of Development at FRAMOS explains the advantages for system designers: "SLVS-EC is the benchmark interface standard of the future for high-speed data transfer from SONY imagers. It uplifts existing and upcoming CMOS designs to the next speed and performance level and supports miniaturization. Each customer using SONY image sensors either working with high-speed or embedded solutions will benefit from the SLVS-EC interface and its unique features. Our RX IP Core Block for Xilinx FPGAs in combination with the full documented evaluation kit makes integration and system development easy, resulting in a faster time to market for customer applications working with SLVS-EC."
FRAMOS said that its RX IP core is the first solution for Xilinx FPGAs on the market, and as an official Xilinx partner, the two companies will work closely together. The SLVS-EC RX IP Core will work with the main existing and upcoming FPGA families and includes the encrypted RTL IP Core with a simulation environment (ModelSim) and dedicated reference implementation examples.
Additionally, FRAMOS suggests that Sony’s new SLVS-EC interface, along with FPGAs, are “key to embedded vision development and allow high-bandwidth and massive parallel processing capabilities while being flexible and efficient.” The SLVS-EC RX IP Core will be released mid-May 2018.