Off-the-shelf signal processors put smart weapons on target

Off-the-shelf signal processors put smart weapons on target

By John H. Mayer, Contributing Editor

Of the US Armed Forces learned anything in the Gulf War it was that devoting Department of Defense resources to smart weapons was money well spent. As recent headlines from the Middle East have proved, the tactical use of smart weapons allows the military to gain a strategic advantage.

Critical to the successful operation of the US Navy`s Tomahawk cruise missiles is the development of accurate and up-to-date terrain maps that guide their flight. An integral element in the mission-planning support of the Tomahawk cruise missile is the Digital Imagery Workstation Suite (DIWS), a stereoscopic image-processing system developed by GDE Systems (San Diego, CA). Designed to generate digital scene-matching area-correlation (DSMAC) reference scenes, the system is used in land-based applications and on four aircraft carriers. Plans call for the system to be deployed on all aircraft carriers and amphibious assault ships.

Precision strikes

The role of the DIWS is to accept and store image data from various tactical and national sources and commercial multispectral data. Together with the Joint Service Imagery Processing System, the system lets Navy commanders plan and execute precision strike missions by using images from any source and format (see Fig. 1).

"The DIWS provides the ability to accept imagery input ranging from government reconnaissance and remote-sensing systems to commercial and casual images, including 35-mm photos, and to produce digital data files for use by automated mission-planning systems on the output side," says Don Bently, GDE Systems manager of advanced programs in the missile planning support area.

Critical to the DIWS success is the real-time delivery of image data regardless of source. To achieve this, the DIWS uses multiple VAX 4000s from Digital Equipment Corp. (Maynard, MA), twenty-six 68030-based single board computers from Motorola (Phoenix, AZ), and three array processors from Mercury Computer Systems (Chelmsford, MA). Included in the hardware pipeline are nine bit-slice processors and more than 140 custom boards. "Hardware is used for many functions because software is not fast enough," explains Bently. The system runs millions of lines of ADA code including algorithms developed for the Defense Mapping Agency (DMA).

Image data are stored on a 48-disk-drive stack that provides 152 Gbyte of on-line storage. Information is then rectified in real time and delivered to multiple workstations. The system photogrammetrically links several images together to extract information.

Although parts of the design are ten years old, the DIWS imaging-processing capability remains formidable. "A geometry engine at the front end of the system is used to interpolate and rasterize images," explains DIWS engineer Christopher Miller. "With typical image sizes of 1k ¥ 1k, we are processing millions of pixels, 60 times a second."

Once images are rasterized, a 7 ¥ 7 convolver either softens the image or sharpens the edges. The system then builds a histogram in real time and drives it into dynamic-range adjustment circuits that add a bias similar to brightness offset. The system also performs contrast adjustment on the image. Finally, data are run through look-up tables to transform the pixel size to 8 bits/pixel for display. A separate processor supports graphics overlays in real-time.

Off-the-shelf DSP

As the Navy plans to mount the DIWS on aircraft carriers and amphibious ships, GDE is upgrading the system to boost performance and reduce space. As part of the development of a new image processor, GDE`s system will display 1k x 1k stereoscopic images at 120 Hz. Driven by commercial off-the-shelf initiatives within the Department of Defense, the system will replace proprietary hardware with off-the-shelf boards. Digital signal processor (DSP) boards will be used for almost all image-processing functions. "Currently our systems are proprietary and we want to change that," explains Miller. The final system will reduce three racks of equipment down to one, while driving processing bandwidths from 17 Mpixels/s to more than 60 Mpixels/s

Earlier this year, GDE Systems turned to Mizar (Carrollton, TX) for help in developing the DIWS image-compression/decompression subsystem called the programmable decompressor. Now, under a $1.1 million contract, Mizar is supplying GDE with its Model MZ7772 DSP board for JPEG and other compression schemes. The single-slot 6U VME board features eight TMS320C40 DSPs from Texas Instruments (Dallas, TX). With each DSP capable of 50 MFLOPs, the board`s aggregate performance is more than 400 MFLOPS.

Raw performance wasn`t the only reason GDE selected the Mizar board (see "Tight interprocessor links boost performance," p. xxx). Each of the board`s C40 DSPs routes two of its six 20-Mbyte/s communication ports to the front panel providing 320 Mbyte/s of data I/O. Other boards based around the Sharc DSP from Analog Devices (Norwood, MA) did not offer comparable I/O management, according to Miller. "In image processing, half the problem is the horsepower of the engine. The other half is moving data," he notes. "The C40 architecture has a balance between the two."

Code compatibility also played a major role. "We didn`t want to go back and rewrite all our algorithms," says Miller.

Dividends in real estate and performance will be formidable. GDE is using a single octal C40 MZ 7772 to replace eleven 9U VME bus boards housing 33 TMS320C30 DSPs. An interface card connected directly into the C40s communication ports links the board to the system`s memory architecture, a 2-Gbit/s time-shared bus. "We are replacing a whole chassis," says Miller. At the same time, performance will increase threefold. While the old subsytem could decompress two 1k x 1k images/s, benchmarks suggest that the Mizar board will deliver six 1k x 1k images/s.

As well as reducing real estate and increasing perfomance, integrating off-the-shelf CPU boards allows map-making and other military systems to be developed faster and at a lower-cost. This benefits the systems integrator, the end user and, in the case of military systems, the taxpayer.

FIGURE 1. GDE Systems Digital Imagery Workstation Suite (DIWS) acts as the centerpiece in the development of digital targeting data for the US Navy`s Tomahawk cruise missile. Soon to be operational on-board all aircraft carriers, the stereoscopic imaging system uses multiple VAXes, CPUs, array processors, and more than 140 custom boards

FIGURE 2. DIWS accepts any input from government reconnaissance and remote-sensing systems to commercial images, including 35-mm photos, and integrates them into one database. Data are supplied to multiple workstations simultaneousl,y and operators use digitized images to create three- dimensional electronic target reference scenes(inset) for smart weapons like the Tomahawk.

Multiple DSPs boost performance

While multiple digital-signal-processor (DSP) configurations have existed for some time, their design has improved radically over the past few years. Improved chip design at the I/O level and the migration by board manufacturers to VME has allowed multiple DSPs to be placed on a single board.

Texas Instrument`s C40 marked a turning point in multiprocessor design. The device`s six parallel communication ports, with independent DMA, mark an improvement over earlier designs. These ports are effective as interprocessor communications channels in multiple processor architectures. The chip`s dual-bus architecture--one local, the other global--has proven ideal for DSP applications. Using the two buses, each connected to separate zero-wait-state memory banks, the TMS320C40 can fetch two external 32-bit words on each instruction cycle offering a peak performance of 50 MFLOPs.

But C40-based board designs vary considerably from vendor to vendor. To achieve maximum performance, the TMS320C40`s local and global memory buses must be connected to separate banks of zero-wait-state SRAM. While most vendors of multiprocessor TMS320C40 boards elect to connect each DSP`s local memory bus to a local SRAM bank, some link together the global memory buses of multiple TMS320C40s to form a single shared global memory bus. With each individual TMS320C40 arbitrating for access to the bus, this approach can create a performance bottleneck.

On Mizar`s 7772, each DSP can be directly linked to as much as 8 Mbyte of zero-wait-state SRAM. Mizar architecture supports direct nonshared connections over both the local bus and the global bus via an optional daughtercard that supports what the company calls near-global memory. Each DSP can also access shared memory over the global bus through a set of transceivers.

To maximize I/O capabilities on the MZ7772 board , Mizar routes two communication ports from each C40 to the board`s front panel. This provides 320 Mbyte/s of data I/O. Moreover, each C40 on the MZ7772 features its own 100-Mbyte/s expansion interface. The board`s VME bus interface is aVME64 master/slave implementation that supports 60 Mbytes/s block transfers over the VME bus.

As part of an upgrade, GDE is replacing 11 VME bus boards housing 33 TMS320C30 DSPs used for image compression and decompression with a single eight-processor TMS320C40-based VME board from Mizar. Key to the MX772 board`s I/O capabilities is the routing of two of each DSPs` six 20-Mbyte/s communication ports to the front panel. The 16 ports (2 ¥ 8 DSPs) provide 320 Mbyte/s of data I/O (inset). In addition, each C40 also features its own 100-Mbyte/s expansion interface.