Reconfigurable arrays: a logical design solution
Reconfigurable arrays: a logical design solution
Andy Wilson Editor
Reconfigurable image processing is a novel technology that`s becoming increasingly important in high-speed vision systems design. In essence, the concept is straightforward. Image-processing operations such as edge detection, morphological analysis, polynomial warping, and Fourier analysis, all involve computing repetitive multiply/accumulate operations. That`s why many image-processing systems use digital signal processors (DSPs) whose architectures are optimized to perform such operations.
Unfortunately, because such DSPs have only a few levels of pipelining, they can only perform so many multiply/accumulate operations before data have to be further processed. A better solution, proposed by several imaging vendors, is a pipeline where specific functions can be added to a data-flow architecture.
Proponents of this more elegant solution include Imaging Technology (Bedford, MA) and Datacube (Danvers, MA), whose products can be used for high-speed image processing. But adding hardwired application-specific modules to this image-processing pipeline can be expensive: each new task--warping, edge detection--requires a new module.
A better solution is to use reconfigurable field-programmable gate arrays (FPGAs) instead of image-processing modules. Intensive computing tasks could be downloaded to FPGAs and run as hardware tasks, increasing throughput and eliminating application- specific tasks.
To implement such systems requires knowledge of the underlying mathematics of the image-processing operation and the means to translate this into hardware. Because this is a complicated software engineering task, many FPGAs are being used to supplement DSPs in vision-systems design.
At last month`s DSP World in Boston, the Xilinx (San Jose, CA) booth was filled with customers who are adopting this approach. While many of Xilinx`s customers have engineered application-specific solutions for graphics, video, and audio, Giga Operations (Berkeley, CA) and Annapolis Micro Systems (Annapolis, MD) showed how Xilinx`s FPGAs can be used for real-time template matching, morphological operations, and various filtering operations. In the PCI and VME boards demonstrated, different operators can be combined to perform more complex imaging tasks than could be implemented in hardware.
Making a choice
Despite this most impressive demonstration, the choice of whether or not to use a reconfigurable processing element in your system may be moot. Some electron microscopy systems that use dumb frame grabbers coupled to PCs do not require real-time performance. Web-inspection systems still require the speed and performance of dedicated gate-array or ASIC-based hardware. And network bandwidth will still remain the limiting factor in medical-imaging-systems design.
But with FPGAs becoming faster and cheaper, and with vendors such as Xilinx and Altera keen to see them in image-processing systems, it probably won`t be long before OEM suppliers are offering the option of reconfigurable image-processing elements. When this occurs, single add-in boards will be able to be used for any image-processing function. But a lot of work still needs to be done. Low-level image-processing algorithms have yet to be ported to run on these devices, let alone high-level user-friendly Windows-based packages. So, if you are thinking of implementing your next OEM imaging board in FPGAs, you may want to wait until the user-friendly software is there to support you.