FIELD-PROGRAMMABLE Gate Arrays BOOST IMAGING PERFORMANCE

FIELD-PROGRAMMABLE Gate Arrays BOOST IMAGING PERFORMANCE

By Barry Philips, Contributing Editor

Field-programmable gate arrays (FPGAs) offer the processing performance of submicron application-specific integrated circuits (ASICs), while providing the design flexibility of reprogrammable digital signal processors (DSPs). When used in vision systems, FPGAs can provide a performance improvement from 30 to 100:1 over their DSP counterparts.

Traditionally, the critical issue regarding whether to use FPGAs or DSPs in an imaging design has been development time. Compared with hand coding an algorithm for execution on a DSP, partitioning a problem into a hardware description for an FPGA takes far longer. But translating algorithms into FPGA hardware increases performance dramatically.

"A customized FPGA design is orders of magnitude faster than software running on a general-purpose processor," says Jane Donaldson, president of Annapolis Micro Systems (Annapolis, MD). Annapolis has used FPGAs to speed edge-detection algorithms for image-analysis applications (see "High-level languages speed reconfigurable development").

New tools needed

Despite these benefits, the complexity of FPGA development has kept large numbers of imaging developers from using the technology. Most developers would rather work at a higher level than FPGA hardware and clock descriptions. Imaging applications typically require the use of mathematical functions such as discrete cosine transforms (DCTs), fast Fourier transforms (FFTs), finite-input-response (FIR) filters, histograms, median filters, morphological filters, two-dimensional convolutions, and tem plate-matching filters.

The Wildfire programming environment that Annapolis Micro Systems provides with its new Wildforce VME board is typical of the tools now being developed to alleviate this complexity. Developers start with VHDL descriptions of the Wildfire computing platform, which consists of four parallel FPGA processing elements connected by a crossbar switch. Algorithms, written as HDL code, are blown into Xilinx gates using Synplicity-Lite from Synplicity (Mountain View, CA).

FPGA board vendor Giga Operations (Berkeley, CA) offers a similar toolkit with a code-generation tool that allows VHDL descriptions to describe the FPGA design. The company is developing a higher-level language description language as part of the toolkit, but admits that it still requires expert knowledge to use it effectively.

For high-density computing, Giga Operations builds small 3.5 ¥ 2.5-in. stackable Xmodules on Xilinx FPGAs. Up to 16 Xmodules can be stacked up and plugged into a single PC-based card to deliver up to 640,000 programmable gates along with 128-Mbyte DRAM and 4-Mbyte SRAM. The company is also building a reconfigurable VME-bus board based on Xilinx FPGAs. An Xmodule with two FPGAs (40,000 gates total), 8 Mbytes of memory, and 256 Kbytes of SRAM is priced at $9400. To demonstrate the effectiveness of the technology, Giga Operations has collaborated with NASA in an imaging system designed to speed data classification of satellite data (see "FPGAs speed satellite data classification").

Morphologic (Nashua, NH) also offers high-level development toolkits for FPGA systems. As one of the first high-level tool suites for FPGA-based image processing, the ArchitectureAdvisor is a functional element library with elements that range in complexity from adders and multipliers to convolutions, DCTs, FIRs, FFTs, and histograms that are ready to be targeted onto FPGAs. According to Charles Furciniti, vice president, "Our tool set gives algorithm developers FPGA design cycles that are 10 to 50 times faster than traditional methods." Morphologic`s approach attacks one of the most difficult problems in reconfigurable computing(it permits signal-processing-based algorithm entry as opposed to register-transfer-level descriptions to be used as input.

Morphologic`s tools attack another weakness in the FPGA design process(the need to run multiple, lengthy design iterations. Typically, an FPGA design must be routed several times before it meets timing and performance requirements. Each routing iteration can take hours and then may not yield acceptable results. Available in the second quarter of 1997 for $2000, ArchitectureAdvisor captures design requirements and ensures they can be met with a single pass of the FPGA router.

Back to school

Staying on the edge of Xilinx technology will require users to reeducate themselves. The company is beta-testing high-level design tools and releasing a new partially and dynamically reonfigurable FPGA architecture, the EX series, that has a microprocessor interface and registers that can be reused by different hardware macros. "In the past, loading new functions meant reprogramming the entire chip. With EX parts, you can add a function while the part is operational. This dramatically improves the use of FPGA resources, says Pierre Popovic, president of MiroTech Microsystems (Saint Laurent, Que., Canada). MiroTech makes a line of DSP acceleration modules called X-CIM that are based on Xilinx FPGAs and a PCI board, dubbed Zippo.

Popovic has built several optimized, ready-to-run functions specifically for imaging. MiroTech`s library includes a 24-tap FIR filter that is 70 times faster than the same code running on a 50-MHz Texas Instruments C40 DSP. MiroTech also has median filters, a 3 ¥ 3 general-purpose convolution, a 5 ¥ 5 symmetric convolution, and a pattern-matching application for1k ¥ 1k images.

Reconfigurable computing continues to drive new hardware developments that will help image processing. The Univision Technologies (Billerica, MA) reconfigurable Falcon-XL image processor brings FPGA-based processing to a board capable of image digitization and display (see "Reconfigurable image processors tackle bomb-inspection tasks"). Pentek (Upper Saddle River, NJ) is building a reconfigurable VME board based on Xilinx parts.

Learning to execute imaging applications on reconfigurable hardware will be a pioneering effort for some time. Mastering partially reconfigurable parts, building up large libraries of imaging functions, and learning to leverage design tools will be a difficult task. But the new levels of price/performance offered by this technology will clearly benefit embedded image processing applications.

Available hardware for reconfigurable image processing includes Annapolis Micro Systems VME board and small 3.5 ¥ 2.5-in. stackable Xmodules based on Xilinx FPGAs from Giga Operations.

Company Information

American Science and Engineering

829 Middlesex Turnpike

Billerica, MA 01821

(508) 262-8700

Fax: (508) 262-8804

Web: http://www.as-e.com

Annapolis Micro Systems

Annapolis, MD

(410) 841-2514

E-mail: [email protected]

Giga Operations

Berkeley, CA

(510) 848-5446

E-mail: [email protected]

MiroTech Microsystems

Quebec, Canada

(514) 956-0060

E-mail: [email protected]

Morphologic

Nashua, NH

(603) 880-4263

E-mail: [email protected]

Pentek

Upper Saddle River, NJ

(201) 818-5900

E-mail: [email protected]

Synplicity

Mountain View, CA

(415) 961-4962

E-mail: [email protected]

Univision Technologies

6 Fortune Drive

Billerica, MA 01821

(508) 667-8900

Fax: (508) 670-1960

E-mail:[email protected]

Web: http://www.tiac.net/users/univis=