FFT processors zip radar, sonar computations
In military- and medical-imaging applications, large data sets must be processed rapidly to obtain high-speed image-recognition results.
In military- and medical-imaging applications, large data sets must be processed rapidly to obtain high-speed image-recognition results. Target tracking, for example, requires the high-speed correlation of target images with unknown imaging data. Performing such fast image processing requires that data must first be transformed from the spatial to the frequency domain (see Vision Systems Design, Aug. 1998, p. 36).
In many systems, optical correlators perform the forward and inverse fast Fourier transforms (FFTs) needed in pattern matching. In systems that do not demand such high speed, DSP-based systems can be used. However, because DSPs are generally multipurpose devices, military systems designers are turning to off-the-shelf ICs that can speed the FFT process by nearly an order of magnitude (see table).
The concept of hardware-specific FFT devices is not new. As far back as 1989, UK-based Plessey Semiconductor introduced the PDSP16510A, a 40-MHz FFT processor capable of performing a 1024-point complex transform in 98 µs. According to Bevan Baas, a postdoctoral research affiliate in the department of Electrical Engineering of Stanford University (Stanford, CA), more than 30 such devices have been implemented both commercially and in research labs; see nova.stanford.edu/~bbaas/fftinfo.html.
DoubleBW (Delft, The Netherlands) has developed a stand-alone FFT chip capable of executing sustained FFT processing and vector multiplication convolutions and correlations on 1-D complex data sets of up to 1k samples. According to the company, the internal hybrid floating-point data format results in more than the single floating-point level of numeric accuracy and dynamic range.
The processing core of the FFT chip is based on four parallel radix-2 butterflies, each running at 128 MHz and a complex multiplier running at 100 MHz. An input register for bit reversal/paralleling the data stream and an output register for serialization allow an I/O data rate of up to 100 MSPS. Capable of supporting a number of data formats through on-chip input and output data converters, the FFT processor can be directly interfaced with analog-to-digital converters (ADCs) and digital signal processors (DSPs).