Compiler maps algorithms

To increase the speed of signal- and image-processing algorithms, researchers are studying reconfigurable computing systems as low-cost ways to increase performance over general-purpose CPUs and digital-signal processors.

To increase the speed of signal- and image-processing algorithms, researchers are studying reconfigurable computing systems as low-cost ways to increase performance over general-purpose CPUs and digital-signal processors. Moreover, in situ reprogrammability means that such systems can be reconfigured on-the-fly for easy modifications. However, this reprogrammability still requires hand coding of image-processing algorithms to perform specific tasks.

To overcome this difficulty, researchers are developing high-level languages and compiler technologies that can automatically map signal- and image-processing algorithms to configurable computing environments. Last spring, Prith Banerjee at Northwestern University (Evanston, IL) described a compiler that takes code from the MATLAB development environment (The MathWorks; Natick, MA) and automatically maps it onto a configurable computer (see Vision Systems Design, April 2000, p. 33).

More recently, Bruce Draper and his colleagues at Colorado State University (Fort Collins, CO) have developed another high-level language, SA-C, for expressing image-processing algorithms and an optimizing compiler that targets field-programmable gate arrays (FPGAs). The SA-C is a variant of the C language designed to exploit both loop-level and instruction-level parallelism in image-processing applications. The SA-C compiler can target either a traditional processor or a host processor with a reconfigurable coprocessor. When targeting a reconfigurable system, SA-C compiles parallelizable loops to logic circuits for the FPGA. Sequential code not inside a loop is compiled to C for the host processor. When compiling loops into circuits, SA-C code is first compiled into a dataflow graph and then into logic circuits expressed in VHDL. A commercial VHDL compiler then maps these circuits into FPGA hardware based on the WildForce board from Annapolis Microsystems (Annapolis, MD).

According to Draper, the goal is to develop an automated programming tool for image-processing applications on adaptive computing systems and to integrate this tool into the Khoros image-processing environment from Khoral Research (Albuquerque, NM). To ensure that the language, compiler, and environment are optimized for image processing, these tools are being developed in conjunction with the vector and signal image-processing library (VSIPL; www.vsipl.org)— an application programming interface defined as an open standard by a consortium of hardware and software vendors, academia, users, and government laboratories. VSIPL has already been adopted by CSPI (Billerica, MA), Mercury Computer (Chelmsford, MA), and Sky Computers (Chelmsford, MA).

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