Clearing up the confusion; Avoiding the issue ...
Clearing up the confusion
While I thank Andrew Wilson for his article covering Intel libraries ("Machine-vision software exploits MMX instructions," Vision Systems Design, Jan. 2001, p. 43), I'd like to make an important correction to avoid confusion. The article refers to the Open Source Computer Vision Library that I run as "CVL" (in fact, it quotes me). I hope I was misquoted, because when I abbreviate our library name, I use "OpenCV" to avoid confusion with the Cognex Corp.'s vision library (CVL), which is trademarked.
The Open Source Computer Vision Library is aimed at creating a market in consumer computer vision, and, as such, contains many routines supporting that area (www.intel.com/research/mrl/ research/cvlib/). Cognex Corp.'s library, CVL, is addressed to machine-vision applications (assembly line inspection, alignment, verification, etc.) and as such contains many specialized and highly optimized routines supporting this area that are well beyond the scope of OpenCV.
Gary R. Bradski
Santa Clara, CA 95054-1537
Avoiding the issue
I enjoyed your article "Machine-vision software exploits MMX instructions"; however, it was marred by an avoidance of an issue.
You went on about differential performance comparisons between MMX based and G4 based systems, using vendor comments about architectures. Then you quoted an AltiVec study by Nicholas Coult on an entirely separate issue.
His study was relevant to the speedup of AltiVec compared to the same computer without AltiVec optimizations. Similar results would be obtained with and without MMX optimizations. Where is the study comparing the effectiveness of AltiVec optimizations to MMX optimizations?
Thus, your article does not help developers choose between the G4-based and Intel PC-based systems and is slightly biased toward G4 systems.
ESI-Vision Products Division
Ann Arbor, MI 48108
You are indeed correct. What would have been really useful is a comparison of the effectiveness of Altivec vs. MMX optimizations, or even one between both these architectures and the new TI devices. Unfortunately, I do not believe one has been published.