Neural networks used in identity degraded binary patterns
Enabling intelligent systems to perform complex reasoning quickly and reliably on large volumes of data is the aim of the Engineering and Physical Sciences Research Council (ESPRC) funded Advanced Uncertain Reasoning Architecture (AURA) project at the Department of Computer Science at the University of York (York, England). Developed in conjunction with the Military Aircraft Division of British Aerospace (Preston, England), the AURA project uses binary neural networks to perform symbolic reasoning and pattern-processing functions.
According to Jim Austin, director of the Advanced Computer Architecture Group at the University of York, a major benefit of the AURA architecture is its support of artificial reasoning with incomplete and uncertain source information. The architecture uses layers of fully connected neurons, known as correlation matrix memories (CMMs), with binary weights. Training the network is accomplished by creating an association between two binary patterns. When another pattern is then applied to the CMM network, the system recalls the trained image, based on the choice of an appropriate thresholding function.
"Depending on the choice of thresholding function," says Austin, "the system can be made extremely robust, even if the input pattern is degraded by noise. Partial matching can then be performed with incomplete data, where some environmental variables may not be present."
However, the aim of the AURA system is not just pattern recognition. A prime objective is to use neural- network technology for symbolic reasoning. In operation, numbers, rules, text, and graphs are converted into binary patterns suitable for processing by the CMMs. In this way, hopes Austin, real-time aids for military aircraft pilots will be developed using incomplete and confusing data.
For some applications, a software implementation of the AURA techniques offers good performance. However, choosing to develop a binary neural-network architecture also allows efficient implementations in hardware to support demanding applications.
Already, the AURA architecture has been implemented on a VME-based board known as Presence. When installed in a Challenge server from Silicon Graphics Inc (SGI; Mountain View, CA), developers can call programs written in C/C++ from the AURA function library that provide access to the VME hardware. According to Austin, this setup allows the hardware to process data up to 200 times faster than using the workstation alone. Further development is being supported by a grant from the EPSRC, which aims to scale the processor for use in pattern-matching problems.
Currently, research is underway to apply AURA for improving address matching for the British Post Office, molecular database searching for Glaxo Wellcome, and other aerospace applications at British Aerospace. For more information, contact Austin at [email protected].
