AUGUST 24, 2007--Tilera Corp. (Santa Clara, CA, USA) has launched the TILE64 processor, the first in a family of tile processor chips based on an architecture that can scale to hundreds and even thousands of cores. The TILE64 processor contains 64 full-featured, programmable cores--each capable of running Linux--and delivers 10 times the performance and 30 times the performance-per-watt of the Intel dual-core Xeon, and 40 times the performance of the leading Texas Instruments DSP. Initial target markets for the TILE64 processor include the embedded networking and digital multimedia markets.
Tilera was founded in 2004 to bring to market the Massachusetts Institute of Technology research of Anant Agarwal, who first created the mesh-based multicore architecture in 1996. The "Raw" project received multimillion dollar DARPA and National Science Foundation grants and spawned the development of the first tiled multicore processor prototype and associated multicore software in 2002.
Tilera's new architecture eliminates the on-chip bus interconnect, a kind of centralized intersection that information must flow through between cores within the chip or before it leaves the chip. As engineers have added more cores to chips, the bus has created an information traffic jam because packets from these cores all must travel to one central point, like a spoke-and-wheel traffic intersection in an old city.
Tilera's technology eliminates the bus by placing a communications switch on each processor core and arranging them in a grid fashion on the chip. This creates an efficient two-dimensional traffic system for packets. Tilera's implementation of this grid architecture is called iMesh (intelligent Mesh). Because the aggregate bandwidth is orders of magnitude greater than a bus and the distance between cores is shorter, the iMesh technology can be leveraged to create grids as large or small as an application requires, creating a "computing-by-the-yard" scalability.
Tilera, a fabless semiconductor company, is the first to introduce a family of mesh-based processors combining a large number of programmable cores on a single chip. Visit www.tilera.com for more information.
