AccelChip and Leopard Logic target DSP market

MAY 28--AccelChip (Milpitas, CA; www.accelchip.com ), an industry provider of automated flows from The Mathwork (Natick, MA; www.mathworks.com) MATLAB algorithms to silicon, has announced that Leopard Logic (Cupertino, CA; www.leopardlogic.com) is the latest participant in its AccelChip Silicon Vendor Alliance Program

MAY 28--AccelChip (Milpitas, CA; www.accelchip.com ), an industry provider of automated flows from The Mathwork (Natick, MA; www.mathworks.com) MATLAB algorithms to silicon, has announced that Leopard Logic (Cupertino, CA; www.leopardlogic.com) is the latest participant in its AccelChip Silicon Vendor Alliance Program (ASAP). Under this agreement AccelChip DSP Synthesis tools will be extended to support Leopard Logic's Gladiator configurable logic devices (CLDs) to offer mutual customers a DSP flow that allows them to take designs from FPGA prototyping into production using Gladiator CLD.

ASAP lets customers evaluate various implementation options from multiple vendors based on a standardized MATLAB tool flow. Under the terms of the program, AccelChip will extend the device-specific optimization engine inside its algorithmic synthesis tool to provide results for Leopard Logic's device family. When combined with AccelChip's AccelWare DPS parametric libraries for signal processing, communications and image processing, designers targeting Gladiator CLD devices will have a top-down, language-based flow for DSP design.

AccelChip supports FPGA, ASIC, and structured ASIC design flows based on synthesis of technology-specific register-transfer level VHDL and Verilog. A version of AccelChip DSP Synthesis with support for the Gladiator CLD devices will be available in June 2004.

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