Active pixel sensors debut at ISSCC

CMOS Active Pixel Sensor (APS) camera-on-a-chip technology was the focus of the Imaging Circuits and Systems session at the 1997 International Solid State Circuit Conference (ISSCC) held last month in San Francisco, CA. Using APS technology, all the controlling, driving, and signal-processing functions of a camera can be incorporated on a single CMOS chip. And at 10-50 mW, the power consumption of the APS sensor is just 1% of CCDs.

Active pixel sensors debut at ISSCC

- BARRY PHILLIPS

CMOS Active Pixel Sensor (APS) camera-on-a-chip technology was the focus of the Imaging Circuits and Systems session at the 1997 International Solid State Circuit Conference (ISSCC) held last month in San Francisco, CA. Using APS technology, all the controlling, driving, and signal-processing functions of a camera can be incorporated on a single CMOS chip. And at 10-50 mW, the power consumption of the APS sensor is just 1% of CCDs.

While CCD imagers require external analog-digital converters (ADCs), compression, and timing support chips, APS devices can also incorporate bias generation, auto exposure, automatic gain control, gamma correction, and output signal formatting for NTSC on-chip. Such high levels of integration reduce cost and weight and permit customization.

Unlike the BiCMOS process used to fabricate CCDs, APS devices can be made using submicron CMOS processes. At ISSCC, Toshiba presented a 330,000-square pixel progressive scan array with 640 ¥ 480 resolution manufactured in 0.6-mm double-polysilicon, triple-metal CMOS. The company plans to shrink the design further to make the device applicable in low-cost, digital still-camera applications.

Researchers at Matsushita (Moriguchi, Japan) and Toyohashi University of Technology (Toyohashi, Japan) integrated a 128 ¥ 128-pixel sensor with two analog 2-D discrete cosine transform processors and a variable quantization-level ADC using 0.35-mm CMOS. The sensor performs real-time 30-frames/s encoding of CIF-format (288 ¥ 352) images.

Polaroid Corp. (Cambridge, MA) also described a current-mode APS architecture capable of 768 ¥ 512 resolution at the conference. Built in 0.8-mm CMOS, the 400,000-pixel APS array operates at 2 frames/s. Polarioid plans to move the sensor design into submicron CMOS and modify the design to attain a higher frame rate. The circuit implements an electronic shutter system that is analogous to the mechanical shutter in a 35-mm single-lens reflex camera. Exposure control is controlled by setting the time between the reset and readout of each row in the array.

It`s still unclear when the APS sensors will become a viable alternative to CCDs soon. Rich Owoc of Sony (San Jose, CA) says it is too early to gauge the impact of APS technology on camera designs. "For the foreseeable future, CCD imagers are the best solution for professionals," he adds.

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