CoaXPress cameras and frame grabbers tackle high-speed imaging

First proposed over six years ago, the now well-established CoaXPress (CXP) camera to computer interface was originally developed by a consortium of Adimec (Eindhoven, The Netherlands), Active Silicon (Iver, England), EqcoLogic (Brussels, Belgium), Components Express Inc (CEI; Woodridge, IL), AVAL DATA (Tokyo, Japan) and NED (Tokyo, Japan).

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With over thirty vendors offering cameras, frame grabbers and peripherals, the CoaXPress (CXP) standard has become the de-facto high-speed machine vision interface

Andrew Wilson, Editor

First proposed over six years ago, the now well-established CoaXPress (CXP) camera to computer interface was originally developed by a consortium of Adimec (Eindhoven, The Netherlands; www.adimec.com), Active Silicon (Iver, England; www.activesilicon.com), EqcoLogic (Brussels, Belgium; www.eqcologic.com), Components Express Inc (CEI; Woodridge, IL; www.componentsexpress.com), AVAL DATA (Tokyo, Japan; www.avaldata.co.jp) and NED (Tokyo, Japan; www.ned-sensor.co.jp).

Awarded the Vision Award at the VISION 2009 trade fair, the standard has now been adopted by over thirty manufacturers of cameras, frame grabbers, and peripheral products. The success of the standard can be attributed to a number of factors.

As an asymmetric point-to-point serial image transmission standard, the CXP standard is scalable. Using a single coaxial cable, downlink speeds of up to 6.25Gbps per cable can be achieved. With a 20.833Mbps uplink for communications and control, the standard also allows 13W of power to be supplied over each cable in Power-over-CXP mode.

Physical interface

Every CXP design features the EQCO62T20 (camera) or EQCO62R20 (frame grabber) CoaXPress transceiver chipset from EqcoLogic. This driver/equalizer combination forms a bidirectional full duplex communication link over a single coax cable and transports 6.25 Gbps over the downlink channel and 20.833 Mbps over the uplink channel. According to Eqcologic, these devices support up to 58m of RG11 co-axial cable at 6.25 Gbps.

While the EqcoLogic chipset forms the physical layer of the CXP standard, camera and frame grabber vendors employ FPGAs for control, protocol implementation and serialization and deserialization. Although many such manufacturers have designed their own FPGA code for such tasks, intellectual property (IP) to aid development of CXP-based FPGA camera and frame grabber interfaces is also available from companies such as Mercury Systems (Chelmsford, MA; www.mrcy.com), Sensor to Image (Schongau, Germany; www.s2i.org), Kaya Instruments (Haifa, Israel; www.kayainstruments.com) and Demand Creation (Nippa Town, Japan; http://dcreation.jp).

The CoaXPress AXI IP Core from Mercury Systems, for example, supports a single downlink of up to 6.25 Gbps for image transfer and a 20Mbps uplink for communications and control. The Core can be implemented on Altera or Xilinx FPGAs and provides 32-bit interfaces for data and control to other FPGA logic (Figure 1).

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Figure 1: The CoaXPress AXI IP Core from Mercury Computer Systems supports a single downlink of up to 6.25 Gbps for image transfer and a 20Mbps uplink for communications and control.

Because the standard is scalable, multiple channels can be used to either support multiple cameras or high speed cameras with multiple CXP ports at speeds greater than 6.25Gbps. For example, single camera implementations running at speeds of up to 6.25Gbps may require a single frame grabber with one CXP port. Dual or quad CXP port frame grabbers can support two or four cameras running at this data rate. Alternatively, single high-speed four port cameras running at data rates of up to 25Gbps can be supported with four channel CXP frame grabbers.

Because of the need to offer systems integrators a range of options, frame grabber vendors currently offer products that support one, two or four CXP ports. Active Silicon, for example, offers its Firebird series of CXP PCI Express frame grabbers with one, two and or four CXP ports while companies such as BAP Image Systems (Erlangen, Germany; www.bapimgsys.com), Bitflow (Woburn, MA; www.bitflow.com) and Matrox (Dorval, Quebec, Canada; www.matrox.com) offer boards with one and two CXP ports (Table 1).

Pg30 Tab1
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In some applications, where multiple, lower speed cameras need to be deployed, a multiplexer can be used to reduce the number of CXP ports required. Because of this, Kaya Instruments has introduced a CoaXPress multiplexer that can simultaneously stream data from up to four CXP camera channels over a single coaxial cable. In operation, the multiplexer handles standard CoaXPress transmission rates and provides bidirectional communication for video, control signals and PoCXP (Figure 2).

Kaya
Figure 2: Kaya Instruments' CoaXPress multiplexer can simultaneously stream data from up to four CXP camera channels over a single coaxial cable.

Form factors

While many CXP frame grabbers are offered in PCI Express form factors, CXP frame grabber functionality can also be added to other form factors such as 6U and 3U VME form factors using FPGA Mezzanine Cards (FMCs).

Designed to provide a modular I/O interface for baseboard or carrier cards, the FMC-CXP from Kaya Instruments, for example, is capable of capturing image data from up to five CXP cameras and is ideally suited to industrial, defense and aerospace applications. This mezzanine card might be also used as camera simulator, emulating up to five transmitting channels. The FMC-CXP also provides isolated GPIO for I/O signals, such as triggers, shaft encoders and exposure control. Each of the five links supports CXP bitrates to 6.25 Gbps and is capable of providing up to 13W of power to compatible devices via Power over CXP (PoCXP).

Camera support

While seven frame grabber vendors now provide support for the CXP standard, the list of camera vendors that offer CXP-compatible products is even more impressive. In January 2013, there were twelve camera vendors offering line-scan, area array and infra-red cameras in a number of different CXP configurations (see "CoaXPress interface standard adopted by camera vendors at VISION show" Vision Systems Design, January 2013; http://bit.ly/XSGB5B).

As of December 2013, four more camera vendors have entered the market (Table 2). These include BAP Image Systems with its LC8K100CXP, a 100k lines/s two-channel CXP camera, three four port area array cameras from Dreampact and the SC 6800 IR dual channel InSb-based IR camera from FLIR (Wilsonville, OR, USA; www.flir.com).

Pg32 Tab2
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Added peripherals

Just as the Camera Link standard spawned a generation of peripheral such as standards converters, high-speed image storage devices and optical extenders, so too has the CXP standard. Systems integrators currently deploying Camera Link cameras, for example, can now take advantage of a Camera Link to CXP converter/CXP to Camera Link converter from Tecphos (Falcon, CO; wwwtecphos.com). In operation, the converter can accept a Base Camera Link output at up to 85MHz and output CXP-3 data at 3.125 Gbits/s over a CXP interface. In this way, the camera to computer distances of Camera Link Base cameras can be extended to 100m.

For those wishing to extend this distance further, Kaya Instruments offers a CXP range extender over fiber that allows CXP camera to computer connections to be extended to distances of up to 10km. Like other fiber extenders, such interfaces are not susceptible to electromagnetic interference, a feature useful in industrial environments. In operation, the camera side converter can provide power to the camera over CXP, while the host side converter can take power from the frame grabber.

With the high data rates provided by the CXP standard, it may be necessary in aerospace or high-speed industrial inspection applications to store image data at high data rates for later retrieval and processing. To meet such demands, IO Industries (London, Ontario, Canada; http://ioindustries.com) has added to its line of digital video recorders (DVRs), the DVR Express Core CXP3. With dual 3.125Gbps CoaXPress inputs and two CXP outputs, the recorder can handle dual-channel cameras, or record from two single-channel cameras. By interfacing the CXP outputs to a frame grabber, camera data can be simultaneous captured and viewed and captured data to be reviewed while image capture proceeds.

While the CXP chipset from EqcoLogic currently supports data rates as fast as 6.25Gbps per channel, release 1.2 of the standard slated for release in fourth quarter 2014 this year will increase the speed of the standard to 12.5 Gbps per cable according to the EMVA (see "CXP aims to run faster" p. 31 of this issue).

CXP aims to run faster

By Chris Beynon, CTO, Active Silicon and Technical Chair for CoaXPress in JIIA.

As part of the recent International camera interface standards meeting in Schongau, Germany, twenty people attended the CoaXPress (CXP) meeting, representing fourteen companies from nine countries. Scheduled for release in Q4 2014, the next version of the CXP standard will ensure that the fastest cameras will continue to operate with CoaXPress.

To date many Version 1.0 products operate with image data rates between 2.0-2.5 GBytes/s (up to 3 times faster than Camera Link Deca). Version 1.1 of the standard also allows the use of a high speed uplink to support line triggers being sent via CXP to a linescan camera at rates above 250kHz.

Speed enhancements for the next version of CXP increase the current maximum data rate per coax cable from the existing 6.25 Gbit/s by adding 10 and 12.5 Gbit/s speeds. This doubles the data rate to 5 GBytes/s using a cable with four coax links, or 7.5 GBytes/s using six links.

Looking ahead 3 to 4 years, however, this may not be sufficient based on the rate of sensor development and customer demands for faster speeds. CXP committee members are therefore investigating options to distribute camera data across multiple frame grabbers, which may be in multiple PCs. This will be more difficult to implement since software features such as automatic discovery and the use of GenICam must be implemented.

CXP currently has a cyclic redundancy check (CRC32) to allow any bit errors to be detected, but there is no mechanism to allow them to be corrected. This is generally not a problem because unlike Ethernet-based systems, for example, CXP is a dedicated point to point link which is nominally error-free. However occasional random single bit errors are possible and options to correct them were considered. Packet resend was rejected, because it gives an unpredictable data rate which would be problematic at the high CXP speeds.

Thus, a forward error correction (FEC) method was considered and a proposal for such a method with a low-implementation overhead is being evaluated. Progress on these topics will be reviewed at the International Standards Meeting in San Jose in Spring this year.

Company Info

Active Silicon
Iver, England
www.activesilicon.com

Adimec
Eindhoven, The Netherlands
www.adimec.com

AVAL DATA
Tokyo, Japan
www.avaldata.co.jp

BAP Image Systems
Erlangen, Germany
www.bapimgsys.com

Bitflow
Woburn, MA
www.bitflow.com

Dreampact
Edinburgh, Scotland
www.dreampact.com

EqcoLogic
Brussels, Belgium
www.eqcologic.com

Euresys
Angleur, Belgium
www.euresys.com

Components Express Inc
Woodridge, IL
www.componentsexpress.com

Demand Creation
Nippa Town, Japan
http://dcreation.jp

FLIR
Wilsonville, OR
www.flir.com

IO Industries
London, Ontario, Canada
http://ioindustries.com

Kaya Instruments
Haifa, Israel
www.kayainstruments.com

Matrox
Dorval, Quebec, Canada
www.matrox.com/imaging

Mercury Systems
Chelmsford, MA
www.mrcy.com

NED
Tokyo, Japan
www.ned-sensor.co.jp

Sensor to Image
Schongau, Germany
www.s2i.org

Silicon Software
Mannheim, Germany
www.silicon-software.de
www.tecphos.com

Vieworks
Gyeonggi-do, South Korea
www.vieworks.com

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