Imaging boards push performance speeds

Frame-grabber-board vendors are implementing the latest interface standards to gain faster operation, throughput, and storage speeds.

Dec 1st, 2002
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In their latest frame-grabber boards, vendors are embracing the newest interfacing standards, such as Camera Link and the 64-bit, 66-MHz PCI bus, to increase the operation, throughput, and storage speeds of machine-vision and image-processing systems. To increase the processing performance of such boards, imaging-specific gate arrays coupled with fast RISC-based processors are off-loading computation from the host computer. And, to rapidly penetrate the PC-based, board-level, machine-vision and image-processing market, vendors are also ensuring third-party camera and software support for PC-based products.

Many PC-based vendors of 64-bit, 66-MHz frame grabbers and image processors are supporting the Camera Link standard, which allows simpler cabling configurations between camera and frame grabber (see the Vision Systems Design Camera Link Special Report, May 2002). As with many frame-grabber designs, such boards can generally be put into three categories. The boards that interface the camera to the PC mainly consist of the most inexpensive boards, and these boards are used to capture images before transfer to the host PC. There are also boards that perform basic image-processing functions and offload processing from the PC; some vendors add preprocessing functions such as look-up tables (LUTs) and programmable gate arrays to their designs.

Finally, there are boards that transfer image data to the host PC. These machine-vision-based boards complement these functions with on-board I/O and camera triggering functions. To completely offload image-processing functions from the host, other vendors have incorporated on-board CPUs, RISC processors, gate arrays, LUTs, and add-in modular display controllers to their offerings. In this way, multiple PC boards can be used to develop very-high-speed, real-time, machine-vision systems.

Gate-array designs

In the past, gate arrays were mainly used to perform functions such as real-time preprocessing of image data—for example, contrast stretching and image filtering. Because of the huge increase in the number of gates now available, today's imaging boards often incorporate these processing functions, PCI-based interfacing, and other performance functions into single devices.

The PCISys and CPCISys imaging boards from PLD Applications (Aix-en-Provence, France) are good examples of such designs. Both the PCI-based PCISys and the CompactPCI-based CPCISys boards use an on-board Apex gate array from Altera (San Jose, CA) to perform data acquisition, parallel multichannel processing, and PCI data transfers up to 64 bits at 66 MHz. With a low-voltage-differential-signaling (LVDS) camera interface and 4 Mbytes of SRAM, the board's PCI programmable interface supports all the features of the PCI-bus standard and provides features such as multifunction, multi-DMA, and embedded-memory controls.

Other examples of such designs include the 64-bit PCI card from Fishcamp Engineering (Orcutt, CA). Designed specifically for Pacific Advanced Technology (PAT; Santa Ynez, CA), the card is offered as part of PAT's Photon series 6000 IR. It consists of a sensor-head module (SHM) that supplies the infrared imager with clocking and bias signals and performs a 14-bit, analog-to-digital conversion of the output video. To provide an interface between the SHM and a host PC, the 64-bit PCI bus uses LVDS drivers and receivers to reduce the number of signal connections and eliminate bulky cables (see Fig. 1).

FIGURE 1. Fishcamp Engineering offers a 64-bit, 66-MHz LVDS card for Pacific Advanced Technology Photon series 6000 IR systems, which consist of a sensor head module that supplies the IR imager with clocking and bias signals and performs a 14-bit ADC of the output video. The 64-bit PCI card uses LVDS drivers and receivers to reduce signal connections and eliminate bulky cabling.
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During operation, this PCI card generates the clock signals to run the camera, stores up to eight different nonuniformity-correction coefficients, and stores contiguous frames of video data. Using an on-board Virtex gate array from Xilinx (San Jose, CA), the board can be reprogrammed to support cameras with up to a 1024 ×1024-pixel format. According to Bob Piatek of Fishcamp Engineering, the card is not currently offered as a standard product, but custom versions have been designed for customers.

"Although the 64-bit bus was introduced on high-end servers," says Colin Pearce, managing director of Active Silicon (Uxbridge, UK), "and as demands increased, it has filtered through to lower-end systems." Like other PCI-based add-in boards, Active Silicon's 64-bit, 66-MHz Phoenix board also uses a Xilinx gate array to support a number of Camera Link-based cameras (see Fig. 2). These cameras currently include the SI3170 from Silicon Imaging (Troy, NY), the C7780-10 from Hamamatsu (Bridgewater, NJ), and the ES 4.0 from Roper Scientific (Trenton, NJ). Running under Windows 98/NT/2000/XP, Mac OS X, Linux, VxWorks, and Solaris operating systems, the board also supports several third-party image-processing packages such as Common Vision Blox from Stemmer Imaging (Puchheim, Germany), Image Pro Plus from Media Cybernetics (Silver Spring, MD), IPLAB from Scanalytics (Fairfax, VA), and LabView from National Instruments (Austin, TX).

FIGURE 2. Active Silicon 64-bit, 66-MHz Phoenix board (top) uses a Xilinx gate array to support a number of Camera Link-based cameras, including the Silicon Imaging SI3170, the Hamamatsu C7780-10, and the Roper Scientific ES 4.0.
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Added power

To offload CPU-based functions from the host PC, many image-processing boards now complement on-board programmable gate arrays with RISC-based processors. In the design of its latest Camera Link-based Max Revolution Pixel Processor, for example, Datacube (Danvers, MA) incorporates a 733-MHz Intel (Santa Clara, CA) X-Scale ARM-compliant CPU with a Xilinx field-programmable-gate-array pipeline processor and up to 1 Gbyte of memory to offload both the host CPU bus of general-purpose processing and the PCI bus from memory data transfers (see Fig. 3).

FIGURE 3. Latest Camera-Link-based MaxRevolution pixel processor from Datacube incorporates a 733-MHz Intel X-Scale AR-compliant CPU with a Xilinx FPGA pipeline processor and up to 1 Gbyte of memory.
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According to Tom Hospod, Datacube vice president of sales and marketing, the board currently supports the 501k, 301bc, and 504k cameras from Basler Vision Technologies (Exton, PA), the Piranha 2 camera from Dalsa (Waterloo, ON, Canada), the MMV2000 camera from Illunis (Minnetonka, MN), and the 1024CL, 640CL, 1320CL, and 6700CL cameras from Pulnix America (Sunnyvale, CA), among others.

"At present," says Hospod, "Datacube is using the A7M266-D 64-bit, 66-MHz motherboard from Asus Computer International (Newark, CA) to test the board." Based on the AMD 762 chipset from Advanced Micro Devices (AMD; Santa Clara, CA), the motherboard and pixel-processor combination currently support third-party machine-vision and image-processing packages that include Halcon and ActiVisionTools from MVTec Software (Munich, Germany) and VideoSavant from I/O Industries (London, ON, Canada) running under Windows 2000/XP.

The board also supports Datacube's Visual CHIP Studio graphical-image-processing algorithm-development software, video-layered-library API software, and MaxRecorder DVR. "Even though the 64-bit, 66-MHz PCI bus is fast," says Hospod, "it is still a bottleneck for image-processing applications, and so-called switched fabric architectures such as RACE++ from Mercury Computer Systems (Chelmsford, MA) could represent a solution for future board-to-board products."

Systems-based approaches

Whereas many companies are designing point products to solve specific machine-vision and image-processing problems, both Coreco Imaging (St. Laurent, BC, Canada) and Matrox Imaging (Dorval, QC, Canada) are taking a more systems-based approach with modular products that embed multiple image-capture, process, and display boards in a single chassis. As part of the introduction of its X64 series of next-generation 64-bit, 66-MHz frame grabbers, for example, Coreco is going to offer a series of modular products designed to interface to analog, LVDS, and Camera Link-compatible standards. Initially, the company is offering the X64-CL series of Camera Link-compatible frame grabbers in two versions: a dual-Base configuration (or one Medium configuration) and a Full configuration (see Vision Systems Design, June 2002, p. 10).

"The X64-CL series two unique features are the acquisition control unit (ACU-Plus) and the data-transfer engine (DTE)," says Philip Colet, Coreco vice president of sales and marketing. The ACU-Plus is a dedicated controller that facilitates image acquisition and pixel formatting and enables images to be captured from two asynchronous digital cameras in independent pixel formats. The DTE uses direct memory access to transfer images and control between the board and the host, allowing features such as variable size and infinite size frames. "When acquiring images from two independent cameras simultaneously, the DTE ensures that the acquired frames are sent to the correct destination buffers in the appropriate pixel formats, allowing vision applications to perform core image-processing tasks more efficiently," he says.

Matrox's next-generation software-compatible machine-vision boards also use a systems approach, incorporating an on-board custom ASIC, a PowerPC, a system interface bridge, and optional analog and digital front-ends on the Odyssey board (see Fig. 4). Like the company's previous-generation Genesis board, the Odyssey board consists of a baseboard and several plug-in modules. Containing a G4 Power PC, up to 1 Gbyte of DRAM, and a custom ASIC called Oasis, the Odyssey board provides a full 64-bit PCI-X architecture that runs at speeds to 133 MHz and delivers burst transfer rates of approximately 1-Gbyte/s to the host PC.

FIGURE 4. Matrox next-generation software-compatible machine-vision boards use a systems approach, incorporating an on-board custom ASIC, PowerPC, system interface bridge, and optional analog and digital front-ends on the Odyssey board. Like the company's Genesis board, the Odyssey consists of a baseboard and several plug-in modules.
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Unlike any other add-in imaging board currently available, the Oasis ASIC, one of the first implementations of the PCI-X interface on an imaging board, incorporates the 64-bit, 133-MHz CPU bus interface to the PowerPC and a 128-bit-wide, 166-MHz double-data-rate DRAM interface capable of transferring image data at rates to 5.3 Gbytes/s. Using 22.4 million transistors, the ASIC also incorporates the next generation of the company's pixel accelerator that, together with the on-board PowerPC, acts as an imaging coprocessor.

"The Odyssey Xpro requires either a 3.3-V conventional PCI slot or a PCI-X slot," says Pierantonio Boriero, Matrox product line manager. "Systems that have these slots feature an Intel Xeon processor with an Intel 840 or 860 chipset (with the P64H 64-bit processor PCI controller hub), an Intel E7500 chipset (with the P64H2 64-bit PCI/PCI-X controller hub), or with a ServerWorks GC chipset. Such slots are also supported by systems that feature an Intel Pentium III with a ServerWorks chipset or an AMD processor with the AMD 760MPX chipset," he says.

In developing a PC-based machine-vision or image-processing system, systems integrators must also match display controllers and other peripherals on the PCI bus. Developers can also choose from a number of new CPU boards, backplanes, network interfaces, graphics cards, and disk interface boards with which to build fully compliant 64-bit, 66-MHz systems. Such peripheral boards will offer greater benefits in I/O-intensive communications, networking, imaging, and storage systems by dramatically increasing bandwidth and efficiency over 32-bit, 33-MHz-based systems. In developing machine-vision systems, however, systems developers must still carefully examine third-party support for camera peripherals and I/O interfacing, and whether 64-bit versions of the host CPU software are available.

"Eventually," says Borierio, "traditional bus architectures will be replaced by switched-fabric architectures. However, the time frame for when these architectures will be readily available is unclear. More time is required to develop a robust and efficient infrastructure for the switched-fabric architecture that outperforms current high-speed buses. Moreover, the computing industry ideally needs to rally behind a single architecture; PCI Express by PCI SIG (Portland, OR), Rapid I/O (which encapsulates RACE++) by Motorola (Austin, TX), and Hypertransport by AMD are all prominent contenders. PCI Express, however, is the most likely to be adopted by the PC industry, and therefore benefit from economies of scale," he adds.

Click here to download "next-generation 64-bit, 66-mhz pci-bus-interface frame grabbers"{pdf size=529kb}.

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