Melding technologies to expand design flexibility

IBM Microelectronics and Xilinx Inc. have agreed to develop novel hybrid chips by early 2004 that combine the attributes of ASIC and FPGA technologies.

Aug 1st, 2002
Th 101836
Click here to enlarge image

IBM Microelectronics (East Fishkill, NY; and Xilinx Inc. (San Jose, CA; have agreed to develop novel hybrid chips by early 2004 that combine the attributes of ASIC (application-specific integrated-circuit) and FPGA (field-programmable gate-array) technologies. Chip designers have long sought a method for configuring multiple circuit functions that allowed changes to be made during and, more important, after the design cycle.

Under the agreement, IBM has licensed FPGA technology from Xilinx for integration into its Cu-08 ASIC products. With as many as eight layers of copper wiring separated by low-k insulation, these products can support up to 72 million wireable gates for developing dense ICs. Now, a large group of gates, generally between 20,000 and 100,000, and possibly as high as 400,000, could be dedicated to one or more FPGA cores on the ASIC. Even after the chip design is customized, the designer still will be able to add functions easily and effectively either using on-chip resources or a traditional programming approach.

In the machine-vision and image-processing industry, for example, many camera vendors are designing in the Camera Link, USB 2.0, or IEEE 1394 (FireWire) interface. All three interfaces use standard off-the-shelf ICs, and some camera vendors are supporting all three interfaces. To do so, however, means re-engineering the back end of the camera for each design. A possible fix, suggests editor Andy Wilson, is tailoring a single FPGA to encompass all three interfaces.

Meanwhile, Coreco Imaging (Billerica, MA; has already taken a step toward such modular products. Built into its X64-CL series of 64-bit, 66-MHz frame grabbers, an FPGA-based ACU-Plus acquisition control unit performs all camera-control functions, such as asynchronous reset, tap reversal, and concurrent acquisition, for multiple format cameras. Programming the unit using the company's Sapera software allows the unit's pixel-packing function to accept data in correct memory-mapped order for the PCI interface.

Combining FPGA and ASIC functions on one chip is expected to result in an extremely flexible array with the density, performance, and overall cost advantages of an ASIC. The combination could cut thousands of dollars off the cost of producing future integrated circuits and eliminate several months of design time.

George Kotelly
Editor in Chief

More in Cables & Connectivity