Andrew Wilson, Editor, [email protected]
At this year's Vision Show West (San Jose, CA), a number of camera and frame-grabber manufacturers introduced products based on the Channel Link specification. Developed by National Semiconductor (Santa Clara, CA), Channel Link uses chipsets that convert data from serial to parallel format and from parallel to serial format for data transmission rates to 2.38-Gbits/s.
In operation, data are serialized by a transmitter chip that converts 28 bits of CMOS/TTL data into four LVDS data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. A receiver then converts the four LVDS data streams back into 28 bits of CMOS/TTL data. At a maximum transmit clock frequency of 85 MHz, 28 bits of data can be transmitted at a rate of 595 Mbits/s per LVDS data channel. Using the 85-MHz clock, the data throughput is 2.38 Gbit/s. Because the standard uses fewer number of conductors than parallel camera interfaces, the interconnection between cameras and frame grabbers is simplified.
Pioneered for use in machine vision by a consortium consisting of Basler-MVC (Exton, PA), Pulnix (Sunnyvale, CA), Coreco Imaging (Bedford, MA), and others, the complete Camera Link specification is now available on the Web at www.machinevisiononline.org. Because some cameras may require several Camera Link ICs to transfer and receive data, the specification details three configurations of the Camera Link interface: base, medium, and full. While the base configuration uses a single Channel Link IC and a single cable connector, the medium configuration uses two ICs and two cable connectors. Last, the full configuration uses three Channel Link ICs and two cable connectors.
Because the specification was only finalized last month, a number of cameras shown at the Vision Show were prototypes. These included line- and array-area cameras that used pins of the LVDS Channel Link interface for power-supply connection. Manufacturers showing these products were quick to point out that these cameras were being re-engineered to support the separate power connector of the finalized specification.
At the show, Basler, JAI America (Laguna Hills, CA), Pulnix, and Illunis (Minnetonka, MN) all introduced cameras based around the standard (see table below). For its part, Dalsa (Waterloo, Ontario, Canada) also showed a number of different linear- and area-array cameras that, according to product manager Mark Butler, were being readied for formal product introduction early next year.
To interface to these cameras, frame-grabber vendors are also scrambling to develop Camera Link-based boards based on the PCI bus. Last June, Alacron (Nashua, NH) became the first company to announce support for the standard, using it on the company's PCI-based frame grabber, the FastImage1300 board. Based on the Philips TriMedia1300 processor, this board is a full-length board that can accommodate up to four such processors, each with 8 to 16 Mbytes of 572-Mbyte/s SDRAM, that each can provide more than 2.6 to 3.6 GFLOPS of computational power.
With a promise of a low-cost Camera Link interface, Euresys (El Cajon, CA) also chose the show to demonstrate its latest product, the PCI-based Dual Camera Link Input module. With two Camera Link compliant connectors, the board can simultaneously acquire data from two gray-scale cameras or multiplexed acquisition from two RGB cameras. The board was shown at the company's booth interfaced to Pulnix's TM-1020 and Basler's L301 and to prototype cameras from Dalsa.
Although the company did not have a working demonstration at the show, DataCell (Finchampstead, Berkshire, England) did show the company's latest PCI-based frame grabber, the Phoenix. According to Kevin Richards, international product manager, the board's scalable PCI DMA engine is capable of supporting both 32-bit/33-MHz and 64-bit/66-MHz PCI buses. Camera Link support for the product will be announced imminently, according to Richards.
