FPGA programming tools allow system developers to rapidly embed image-processing algorithms.
Developers of high-performance frame grabbers and image-processing boards have sought to optimize the throughput of their products using dataflow architectures inherent within FPGAs. To optimize image-processing algorithms most effectively, developers often tailor their algorithms in hardware description languages (HDLs) such as Verilog and VHDL. Once described in this way, the programs can be compiled into register-transfer-logic net lists, synthesized into logical gates, then placed and routed and embedded into the FPGA.
