Technology Trends: CMOS imagers address fixed-pattern nonuniformity
When compared to charge-coupled devices (CCDs), complementary metal-oxide semiconductor (CMOS) imagers suffer from fixed-pattern nonuniformity (FPN) caused by mismatches in their device parameters.
When compared to charge-coupled devices (CCDs), complementary metal-oxide semiconductor (CMOS) imagers suffer from fixed-pattern nonuniformity (FPN) caused by mismatches in their device parameters. To reduce this noise, many CMOS-imager vendors use correlated-double-sampling techniques to improve the signal-to-noise ratio of their devices. This approach subtracts the imager's signals from a reference level, reducing FPN and several types of temporal noise.
"Most active-pixel-sensor (APS) developers are working to develop postprocessing methods to correct this fixed-pattern noise problem," says Tom Vogelsong, president and chief executive officer of Photon Vision Systems (PVS; Cortland, NY). "While some are using complex off-chip circuitry and algorithms to perform offset and gain correction per pixel, others are adding more on-chip circuitry either at the pixel or at the periphery," he adds.
In the design of its active-column-sensor (ACS) imager, PVS uses a unity gain amplifier at every pixel to reduce FPN. At PVS, the inventors of the ACS, Jeff Zarnowski and Matt Pace, realized that each unity gain amplifier would require six or more field-effect transistors (FETs) to implement, result in a greatly reduced fill factor, and double the device's complexity with reduced yields and increased costs.
In overcoming these limitations, Zarnowski and Pace recognized that all but the input FET of each unity gain amplifier for each pixel of a column was redundant. Accordingly, they placed five of the six FETs at the end of a column-therefore, the term active column sensor and not active pixel sensor. These FETs are shared by all the pixels along that column (see figure). Therefore, only one dual-gate FET is needed at each pixel of a column.
"While active pixel sensors need three or more transistors at each pixel, active-column-sensor devices need less circuitry," says Vogelsong. "And when coupled with a correlated-double-sampling circuit to remove offset variations, this design leads to a higher fill factor, greater sensitivity, and higher yield."
FIGURE: By implementing a unity gain amplifer (UGA) at each pixel, PVS engineers claim to have reduced the level of fixed pattern non-uniformity in CMOS sensors. Cleverly, five of the six FETs used to implement the UGA are located in an active column, resulting in an increased fill factor of the photosensor site.
PVS plans to offer this technology in a number of devices including monochrome and area-array devices that range from 640 x 480- to 1280 x 1024-pixel-resolution imagers with 7.8 x 7.8-µm pixel sizes. Fabricated in a 0.35-µm CMOS process, the devices are expected to feature a fill factor of 60% and 10-bit digital outputs.
Whereas many imager vendors tout the benefits of "standard" CMOS processes as means to reduce cost, the advent of submicron geometries will make them more difficult to fabricate, according to Hon-Sum Wong of the IBM Watson Research Center (Yorktown Heights, NY). "While standard CMOS technologies provide adequate imaging performance at 1-2 µm, modifications to the CMOS process are needed to enable the CMOS process to perform good-quality imaging at 0.5 µm and below," he states.
What's more, that's exactly the geometry that will be needed to attain moderate- to high-resolution imagers of 1k x 1k pixels. "Indeed," says Wong, "using standard CMOS technologies for imaging does not automatically result in significantly lower cost." In the end, the main benefit of using CMOS for solid-state imagers is expected to be the level of systems integration that can be attained on chip, rather than the quality of the image produced.