Silicon Hive and Apical Imaging develop embedded imaging for mobile devices

FEBRUARY 6, 2008--Silicon Hive (Eindhoven, The Netherlands) and Apical Ltd. (London, UK) have entered into a partnership agreement to jointly develop solutions for (mobile) camera phones.

FEBRUARY 6, 2008--Silicon Hive (Eindhoven, The Netherlands; and Apical Ltd. (London, UK; have entered into a partnership agreement to jointly develop hardware accelerated retina-morphic and image signal-processing solutions for (mobile) camera phones and other terminals with demanding imaging requirements. The agreement calls for Apical to optimize and port several of its image-enhancement and processing engines to Silicon Hive's HiveFlex ISP 2200 programmable processor. Silicon Hive will enhance its HiveFlex ISP 2200 processor's instruction set for Apical Imaging's engines resulting in area and power efficient silicon designs.

The first joint product ready now for evaluation is the Apical Iridix engine running on a HiveFlex ISP 2200 processor. The companies will be showing live demonstrations of this new product at the Mobile World Congress in Barcelona Spain, February 11--14.

Iridix is a sophisticated method of dynamic range compression that has already been widely adopted by leading DSC manufacturers. It differs from conventional methods such as gamma correction in that it applies different tonal and color transformations to every pixel in a source image. It is based on research into the human visual system and, in particular, mimics the way in which the human retina adapts to scenes of high and variable contrast.

The HiveFlex ISP 2200 processor can process more than 100 Mpixels/s. It is C programmable and easily scaleable to meet varying needs of either CMOS image sensor or imaging SoC manufacturers. The five issue slot architecture combines VLIW and SMID vector functions that can be scaled, for example, in the number of bits per pixel, data path, SIMD vector size, and other dimensions. The HiveFlex ISP 2200 is based on Silicon Hive's parallel-processing technology. It uses proprietary data, instruction, and task level parallelism to achieve area and power efficient designs not found in other common DSP like design.

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