Increasing Vision Performance by Preprocessing on the Frame Grabber

manufacturers and vision integrators to upload code to the FPGA in the company’s Coaxlink Octo and Coaxlink Quad CXP-12 frame grabbers to handle image processing tasks that would otherwise have to be performed on the host. The Euresys CustomLogic FPGA design kit can handle virtually any repetitive image preprocessing task that is performed on every pixel of the image. Typical applications include transforming the image based on a lookup table such as by converting the color from the RGB to the YUV scale, implementing a noise reduction algorithm, and compensating for sensor defects such as black pixels. Another common application is flat field correction, compensating for differences in light intensity over the field of view.Performing image processing on the frame grabber provides dramatic improvements in image quality and processing speed, particularly for cutting-edge vision systems that are currently bottlenecked by the processing power of the host computer. The FPGA processes the image in parallel with image transfer so processing time savings on the host computer are achieved without adding any delays in the frame grabber. This means that vision systems can deliver higher resolution, higher image speeds and lower latency without increasing the cost of the host computer.In the past, frame grabber suppliers have offered to incorporate their customers’ code into their FPGAs at the heart of their frame grabbers. This approach requires that users share their proprietary intellectual property so that it could be designed into the frame grabber. In the new CustomLogic approach, on the other hand, users create and compile their own FPGA code into an object file and then upload it to the FPGA using a tool provided by the frame grabber company.The vision integrator’s proprietary code never leaves its premises and the resulting FPGA would be extremely difficult and expensive to reverse engineer.Many large machine makers have developed their own frame grabbers based on FPGAs that also perform image processing and analysis tasks. These frame grabbers in virtually every case use the venerable Camera Link protocol. The machine makers that designed them are now faced with the difficult challenge of redesigning the frame grabbers to accommodate the current generation of high-speed interfaces such as CXP-12. Their task can be greatly simplified by taking advantage of the built-in CXP interface and ability to upload their proprietary image processing routines offered by the new Euresys frame grabbers.The CustomLogic FPGA design leaves up to 70% of the resources on the Xilinx Kintex Ultrascale XCKU035 FPGAs used in the Coaxlink Octo and Coaxlink Quad CXP-12 frame grabbers for image preprocessing.