Pleora and imavix Partner to Advance GigE Vision 3.0 with High-Speed, Deterministic Ethernet Solution

Vision Systems Design wanted to find out more, so we reached out to James Falconer, product manager, Pleora Technologies and Jan Pech, CEO, imavix engineering with some questions.

Editor’s note: The following Q&A may have been edited for style and/or clarity.

Vision Systems Design (VSD): GigE Vision has long relied on UDP transport. At 10 and 25 Gbps, where do traditional UDP based pipelines begin to break down, and why did Pleora and imavix determine that RoCEv2 was necessary to maintain determinism and low latency?

James Falconer (JF), Product Manager, Pleora: It’s important to note that RDMA over Converged Ethernet version 2, or RoCEv2, is a key capability in the evolution of the GigE Vision standard. 

At higher link speeds, the best-effort limitations of the existing GigE Vision Streaming Protocol, which is based on UDP, become apparent. At 10 and especially 25 Gbps and beyond, packet rates are high enough that OS scheduling effects, interrupt handling, and buffering introduce latency variability and jitter. While earlier versions of the GigE Vision standard’s resend capability preserves data integrity, it reduces determinism for applications that depend on consistent timing while also consuming additional memory on the host PC.

GigE Vision 3.0 introduces RoCEv2 as a standards‑based transport option, enabling direct delivery of image data into host memory with no CPU involvement. By defining this capability within the standard, GigE Vision 3.0 maintains interoperability while enabling predictable, low‑latency performance at 10 and 25 Gbps and provides a scalable foundation for future bandwidth increases.

Jan Pech (JP), CEO, imavix engineering: From a system and application perspective, the core issue is timing consistency and availability of processing resources. At 10 and 25 Gbps, variability introduced by the host networking stack becomes visible with standard GigE Vision over UDP. Even infrequent re-sends can disrupt tightly synchronized real time vision devices and systems. With increasing data rates, the legacy packet resend mechanism becomes very inefficient, as devices need to maintain large transmit frame buffers what has impact on device BOM, product size, cost, and power consumption. With the reliable data delivery of RoCEv2 which is ensured at the hardware level, any optional retransmission is immediate and does not require external DDR memory for transmit buffers.

RoCEv2 provides a controlled data path that removes packet handling from the CPU. That makes Ethernet based vision behave deterministically at high speed, which is increasingly important as vision data feeds directly into real time decision and control systems.

VSD: This solution tightly integrates FPGA based GigE Vision 3.0 IP with Pleora’s host side eBUS SDK. From a system design standpoint, what advantages does this end to end approach offer compared to assembling discrete FPGA, NIC, and software components?

JF: The advantage of an end to end approach is consistency across a standards defined pipeline. Device discovery, control, events, and stream negotiation behave exactly as defined by GigE Vision and are implemented in a way that is compliant rather than proprietary. This reduces integration risk and shortens development time, while ensuring compatibility with existing GigE Vision processes, applications, and workflows.

JP: When discrete components are assembled independently, each tends to make assumptions about buffering, timing, and flow control that were never designed to align. Resolving those mismatches is manageable at lower speeds but becomes significantly more complex as bandwidth increases.

An integrated pipeline with the imavix IP Core and Pleora’s eBUS SDK removes that ambiguity. The IP Core, transport mechanism, and host software are designed to operate together as a single system. For architects, this reduces custom tuning, lowers integration risk, and results in more predictable performance from the first prototype to production.

VSD: By enabling direct device to host memory transfers that bypass the CPU, how does the integrated pipeline change the way system architects should think about latency budgets, CPU utilization, and real time performance margins?

JF: With GigE Vision 3.0, the CPU is no longer in the critical data path for image transfer, which makes latency and jitter more predictable. CPU resources remain available for application logic, while high bandwidth data movement is handled efficiently and deterministically via GigE Vision 3.0’s adoption of RoCEv2.

JP: The key change is not just lower latency, but lower variability. When the CPU is removed from the data path, architects no longer need to design around worst‑case spikes caused by packet handling or resends.

This allows tighter and more realistic latency budgets. CPU resources can be allocated to application processing rather than overprovisioning the system, and real‑time performance improves because uncertainty has been engineered out of the data path.

I would like to emphasize that the “host memory” does not necessarily mean the main memory of a computer. It can be any memory region within the host system. 

VSD: As vision systems push beyond 25 Gbps, what parts of the imaging pipeline become the most difficult to scale, and how does this joint solution address that?

JF: As bandwidth increases, a challenging part of the pipeline to scale is the host side receive path. Traditional, software based packet processing for GigE Vision over standard UDP places increasing pressure on the CPU for packet handling, buffering, and memory copies. At 25 Gbps and beyond, this is inefficient and introduces latency variability and jitter, which directly impacts determinism at the application level.

With our integrated solution we’re moving the high bandwidth data path out of the CPU. Image data is transferred directly into application memory using RDMA, while eBUS continues to manage the GigE Vision control, stream configuration, and synchronization in a standards compliant way. From a system perspective, this means the receive architecture scales with network bandwidth without requiring code changes or extensive host tuning. 

JP: At very high data rates, CPU performance becomes a limiting factor, particularly when deterministic data delivery is required. Simply adding more CPU resources does not scale and increases system complexity and costs.

This solution addresses those challenges. The GigE Vision 3.0 IP Core implements a deterministic, standards compliant transmit path directly in the FPGA, ensuring consistent timing and flow control at the source. Combined with RDMA capable NICs on the host and eBUS SDK, image data is transferred directly into memory with minimal CPU involvement. The FPGA IP core itself offers scalability for the user, keeping all the interface protocols and control paths backwards compatible (newer versions can still work with older versions of software, hardware, data, or standards). Very simply, upgrading a device to higher Ethernet link speed requires use of different configuration of the IP core with wider data input interface, but no conceptual changes of the device FPGA design.

The result is that data movement and synchronization scale with link speed without requiring changes to the application layer. System designers can increase bandwidth while preserving the same GigE Vision control model and host software interfaces, which is essential for long term scalability and system evolution.

VSD: For integrators building complex systems, what practical impact does this predictable, standards aligned pipeline have on system integration time, long term maintenance, and upgrade paths?

JF: Predictable, standards aligned behavior reduces integration time because systems are easier to validate and debug. Integrators can continue using established GigE Vision tools for control and diagnostics, even as performance increases.

Over the long term, standards compliance provides a clear upgrade path as new devices and higher speed links are introduced.

JP: From an integration and lifecycle perspective, predictability directly reduces cost and risk. Integrated, standards-compliant solutions result in imaging devices or systems that behave consistently and are easier to validate, reproduce, and support over time, particularly in complex, multi‑device vision system architectures.

Just as important, a standards‑based pipeline provides a clear and low‑risk path to higher bandwidths. Because the data transmission and host interfaces remain consistent as link speeds increase, designers and integrators can scale from today’s deployments to higher‑performance systems without redesigning their application software or system architecture.

This allows bandwidth upgrades to be treated as incremental system evolutions rather than disruptive platform changes. Existing investment in software, validation, and operational knowledge is preserved, which simplifies scalability and enables systems to grow in capability as performance demands increase.