Spotlight on reconfigurable imaging: Programmable logic matches reconfigurable imaging to system demands

Programmable silicon building blocks allow designers to equate specific imaging-application requirements so that working platforms are produced faster and easier.

Dec 1st, 1999
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Programmable silicon building blocks allow designers to equate specific imaging-application requirements so that working platforms are produced faster and easier.

By Andrew Wilson,Editor at Large

Although microprocessors have dominated general-purpose computing, certain image-processing functions can be more efficiently performed in custom or programmable logic devices. These devices can offer a much higher computational efficiency than their CPU counterparts while at the same time offering systems designers the ability to program in situ.

For routine computations, such as the fast Fourier transform (FFT), reconfigurable architectures offer a clear superiority over general-purpose processors. On the other hand, if a vision system is required to perform multiple, diverse image-processing tasks, designers should consider programmable digital-signal processors (DSPs).

Market-research firm IC Insights (Scottsdale, AZ) forecasts that the programmable logic device (PLD), dynamic random access memory (DRAM), and flash memory product segments will all grow at more than twice the rate of the IC market this year (see Fig. 1). According to this forecast, the primary beneficiaries in the PLD segment are the established leaders Altera (San Jose, CA) and Xilinx (San Jose, CA).

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FIGURE 1. Market-research firm IC Insights forecasts that the PLD, DRAM, and flash-memory product segments will grow at more than twice the rate of the IC market this year. According to the company, the primary beneficiaries in the PLD segment are Altera and Xilinx.

As PLD vendors add more functionality to their devices, a number of them, including Altera, Xilinx, Integrated Silicon Systems (ISS; San Jose, CA), Technical Data Freeway (Concord, MA), and MoTarg (Austin, TX), offer intellectual-property (IP) cores to imaging developers. As a fast way to implement edge detectors, finite impulse response (FIR) filters, Joint Photographic Experts Group (JPEG) encoders and decoders, NTSC/PAL encoders, FFTs, and video motion-tracking systems, these cores are often available for application-specific integrated-circuit (ASIC), field-programmable gate-array (FPGA), and complex PLD (CPLD) implementations (see table on p. 40).

To address the issues of time to market, performance, power consumption, and silicon area, companies such as ISS have developed a range of libraries for image processing and other functions. These libraries consist of synthesizable building blocks for ASIC, FPGA, and CPLD implementations optimized for each technology. "Such building blocks mirror in silicon the techniques used in software design and allow functions to match the specific requirements of each application in terms of performance, data word lengths, function accuracy, and control," says Doug Ridge, ISS director of business development. "The ability to set function parameters prior to synthesis and the ease of use of the building blocks ensure that working solutions are produced rapidly, reducing product time to market," he adds.

Imaging finds FPGAs

Lower production volumes and shorter product life cycles are typical for many image-processing devices used in machine-vision, barcode inspection, and medical-imaging applications. Rather than incur the cost of full custom designs, developers are turning to FPGAs to process real-time image data through two-dimensional, FIR filters, infinite impulse response (IIR) filters, and other imaging algorithms.

In the development of its ShapeGrabber add-in PC board designed for laser scanning, for example, Vitana (Ottawa, Ontario, Canada) needed to build a turnkey vision system for manufacturers to inspect and develop complex parts in three dimensions. This system includes a scanning head, translation stage, acquisition and inspection software, and PC. In operation, the ShapeGrabber can acquire 15,360 points/s with a measurement accuracy of 0.001 in.

To control and implement the digital-signal processing algorithms of the ShapeGrabber, Andrew Nelson, a hardware engineer with Vitana, based the design around a TMS320C44 floating-point DSP from Texas Instruments (Dallas, TX). To provide real-time video digital-signal processing for 3-D data, the design demanded real-time video peak-detection and subpixel interpolation (see Fig. 2).

"Gate arrays, off-the-shelf programmable filters, and PLDs could have been used in the design," says Nelson. "But, although gate arrays can be less expensive in volume, their long development times made them unsuitable," he adds. "We also considered using FPGAs with segmented routing, but ultimately decided against them because of their poor routability and our need to guarantee timing and fitting with each design iteration," he says.

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FIGURE 2. To provide real-time video DSP for 3-D data, system design, including a scanning head, translation stage, acquisition and inspection software, and PC, demanded real-time video peak detection and subpixel interpolation implemented in Altera PLDs.

"Designing the video peak- and subpixel interpolator was the most challenging task," says Nelson. The design-which includes two FIR filters-was implemented in an Altera EPF81188A programmable logic device. The peak locator was a 16-bit, 8-tap filter, and the peak location validator was a 14-bit, 3-tap filter. Both filters ran at video rates. The design also contained a subpixel interpolator. In this design, Nelson used the Altera Max+Plus II 6.0 software-design environment, which supports a library of parameterized modules to create custom building blocks.

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FIGURE 3. Programmable logic devices are used to perform the high-pass filtering needed to accentuate the edges in the captured image of information barcode symbols such as UPC, Postnet, Code 39, PDF-417, and Data Matrix.

"One feature of the ShapeGrabber allows upgrades and modifications to be performed in the field," says Nelson. "This was accomplished by reconfiguring the Flex 8000 devices over the PCI bus," he says. To do so, Nelson wrote a software driver that converts a Flex 8000 programming file to configuration data and downloads this data to the Flex 8000 device over the PCI bus on startup. "All that is required for upgrades is a single, new programming file that can be sent to the customer electronically," he adds.

Barcode scanning

Reducing costs while creating a scalable design was also the reason Ken Coffman, an engineer with Intermec (Everett, WA), gives for the design of programmable logic in the companys range of CCD-based scanners. Developed to read information symbols ranging from barcodes such as UPC, Postnet, and Code 39 to two-dimensional codes such as PDF-417 and Data Matrix, the scanners can read all these code in any orientation (see Fig. 3).

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To perform the high-pass filtering needed to accentuate the edges in the captured image of an information symbol, Coffman implemented ann x m transformation function that multiplies the incoming image data by a set of filter coefficients and sums the results. In the scanner, the filter implements a spatial finite impulse response filter with a 3 x 3-filter kernel. The filter uses a center pixel and its eight neighbors to calculate the value of a new pixel. The new pixel value is calculated by multiplying the input pixels by the coefficients in their respective kernel positions and summing the results.

To make the coefficient multiplication faster and less resource-intensive, Coffman used the fact that, in binary representation, multiplication by integers that are powers of two is the equivalent of shifting the entire binary representation one place to the left. As a result, Coffman replaced all of the multipliers in the filter with shift registers and other logic. "This approach," says Coffman, "resulted in a design with about 60% fewer device resources than a traditional design using full multipliers."

Targeting defense

"A key defense problem involves locating and identifying potential targets," says José Muñoz, assistant director for embedded and autonomous systems at the DARPA Information Technology Office (Fairfax, VA). "This process involves searching 40,000 square nautical miles per day with a 1-m-resolution device-the equivalent of locating an object several meters in diameter in an area the size of a small country."

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FIGURE 4. Annapolis Micro Systems WASSP system (top) uses a progressive-scan, digital, CCD ES 310 MegaPlus camera from Eastman Kodak (San Diego, CA) to digitize 648 x 484-pixel images at 85 frames/s. An image-processing application performs gradient edge detection, adaptive thresholding, and line finding.

Challenged with developing and exploiting reconfigurable computing for evolving defense systems, Muñoz and his group turned to Annapolis Micro Systems (Annapolis, MD). This company developed a hybrid computing engine,WASSP (Wildforce-based Adaptive Signal Processing Project), that uses an FPGA-based computer and a DSP.

To perform image processing, the WASSP system uses a progressive-scan, digital CCD ES 310 Megaplus camera from Eastman Kodak (San Diego, CA) to digitize 648 x 484-pixel images at 85 frames/s. Included with the system is an image-processing application that performs a gradient edge detection, an adaptive thresholding algorithm, and a machine-vision-operation (line-finding) algorithm (see Fig. 4). The gradient edge-detection algorithm is implemented using an FPGA-only approach, while the line-finding algorithm uses an FPGA/DSP-hybrid approach.

Because of their flexibility, FPGAs have become a key element in image-processing systems in which flexible camera interfaces and reconfigurable image processing are required. As well, they have found widespread use in general-purpose CPU designs where they are replacing much of the glue logic once found on CPU motherboards.

"Some new imaging uses harness large numbers of FPGAs as a general-purpose computation medium," says Scott Hauck, assistant professor, department of electrical and computer engineering, Northwestern University (Evanston, IL). "While these FPGA-based custom-computing machines might not challenge the performance of microprocessors for all applications, for computations of the right form, FPGAs can offer extremely high performance, surpassing any other programmable solution," he adds.

"Although a custom hardware implementation should beat the power of any generic programmable system, few applications ever merit the expense of creating application-specific solutions. An FPGA-based computing machine, which can be reprogrammed like a standard workstation, offers the highest realizable performance for many different applications," Hauck says.

Company Information

Annapolis Micro Systems
Annapolis, MD 21401
(410) 841-2514
Fax: (410) 841-2518

Department of Electrical and Computer Engineering
Northwestern University
Evanston, IL 60208

Intermec Technologies
Everett, WA 98203-9280
(425) 348-2600
Fax: (425) 355-9551

Texas Instruments
Dallas, TX

Video Perception
Indianapolis, IN 46201-2526
(317) 972-7916
Fax: (317) 231-9680

Ottawa, Ontario,
Canada K1H 1E1
(613) 247-1211
Fax: (613) 247-2001

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