Vertical transistor doubles chip processing speed
In their quest for chip miniaturization, researchers at Lucent Technologies (Murray Hill, NJ; www.lucent.com) have developed a revolutionary 50-nm silicon transistor. They call the chip a "vertical" transistor because all of its components are built on top of a silicon wafer and its current flows upward. Conventional transistors typically measure 180 nm, they are formed within the silicon wafer, and their currents flow horizontally. In addition, a conventional transistor contains only one gate, which switches current on and off. The vertical transistor resembles a rectangular block with a gate on each of two opposing sides. Consequently, this new design holds the promise of doubling the processing speed of some silicon chips.
Lead Bell Labs (www.bell-labs.com) researcher Jack Hergenrother says, "Our vertical transistor eventually could supersede the conventional transistor, which many experts in the semiconductor industry anticipate will hit a brick wall within the next ten years." Semiconductor companies now use light to pattern features on silicon chips. However, as transistors continue to shrink in size, most experts agree that light eventually will be unable to produce the smaller features needed, especially the gates. Moreover, gate size varies considerably when the light method is used; therefore, chips must be designed to tolerate this variation, which diminishes overall chip performance.
The vertical transistor approach solves these problems by using the thickness of a precisely controlled layer of material, rather than light, to set the gate size. The technology for producing extremely thin, uniform, and reproducible layers of materials is well developed in the semiconductor industry. This means that today's manufacturing facilities can be implemented to produce the vertical transistor in volume without major retooling.
Explains Hergenrother, "Suppose you have a can of paint and a big paintbrush and you're asked to paint the thinnest possible line. If you tried to paint the line freehand, that would be similar to the light approach. However, if you paint a flat surface, cut it vertically, and look at it on edge, you will see a line that's as thin as the layer of paint. A similar principle is used in our transistor to produce the smallest gates ever made with the control that industry requires."
Based on the present vertical transistor's 50-nm gate, the Lucent researchers believe that they can soon produce 30-nm gates. The vertical transistor's design also might help forestall another challenge faced when making smaller transistors-the shrinking insulating layer. This layer, which lies between the transistor's gate and the current-flow channel, prevents short circuits. However, these insulating layers are becoming so thin that electrons might pass through and cause device breakdown. As a result, the semiconductor industry is trying to discover alternative materials for the insulating layer for replacing today's silicon dioxide.
Another major design obstacle to potential layer material replacement concerns the high temperatures encountered in the semiconductor manufacturing processes. The vertical transistor design eliminates this problem because the gate and the insulating layer are applied last in the manufacturing process, after all the high-temperature processes are completed.
Adds Mark Pinto, chief technical officer, Lucent Microelectronics Group, "This groundbreaking research provides new opportunities for integrated circuit miniaturization and performance enhancement. Recently, there has been much concern that the semiconductor industry will soon encounter fundamental limits to how small and fast we can make transistors. This research clearly provides new ways to tackle these challenges."
The Bell Labs approach provides several advantages over previous designs. It can accommodate ultrathin insulating layers, and the channel and gate are closely aligned. What's more, it may be possible to add additional layers of transistors to silicon chips, resulting in so-called "high-rise" chips.
Dimitri Antoniadis, professor of electrical engineering at the Massachusetts Institute of Technology (Cambridge, MA), comments, "This is the best demonstration of vertical technology to date."
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