FEBRUARY 4--Hitachi Ltd. (Tokyo, Japan; global.hitachi.com) and the Microsystems Technology Laboratories of the Massachusetts Institute of Technology (MIT; Cambridge, MA) have jointly developed a new circuit concept for digital-signal processors that will help to realize minimum power processing for system LSIs, such as those used in personal digital assistants. The technology was applied to a multiply-accumulate unit used in signal-processing LSIs, and operation was confirmed for a 100-mV supply voltage, which is considered to be the theoretical limit of low supply voltage in CMOS circuits at room temperature.
Lower power consumption continues to be a vital need in system LSIs, which are the core of mobile multimedia devices such as note PCs, personal digital assistants and cellular phones, in order to extend battery lifetime. Generally the most-effective way to achieve this is to decrease the supply voltage, however, low-voltage operation also degrades LSI performance. Thus, the simultaneous achievement of both high performance and low power has been an important goal.
To tackle these issues, Hitachi and MIT have been independently researching the development of low-power-circuit technology--Hitachi working on body bias control and MIT on supply-voltage-control technology, in relation to current LSI operating frequencies. Hitachi and MIT joined forces to cooperate in their research efforts to achieve even lower power consumption. The collaboration has resulted in the successful development of technology that approaches the theoretical limit of low power operation.
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This low-power system LSI technology will be presented at the International Solid State Circuits Conference in San Francisco, CA, this week.
