New processors push imaging performance

Despite their flexibility and relatively low cost, field-programmable gate arrays (FPGAs), do not provide the performance of much more expensive custom-built application-specific integrated circuits (ASICs).

Andrew Wilson, Editor, andyw@pennwell.com

Despite their flexibility and relatively low cost, field-programmable gate arrays (FPGAs), do not provide the performance of much more expensive custom-built application-specific integrated circuits (ASICs). Recognizing this, a number of semiconductor vendors have recently announced products that fall between FPGAs and ASICs in both performance and price. These custom-reconfigurable processors use different architectures to exploit the parallelism inherent in image-processing functions. Usually programmable in high-level languages, they allow system designers to increase the performance of their systems while at the same time not incurring the time to market and cost penalties of ASICs.

Often called adaptive computing elements, the architecture of these processors is, from a high level, often very similar. An array of thousands of either single-instruction multiple-data or multiple-instruction multiple-data processing elements is linked with RAM and I/O elements that are fed by an internal or external RISC core processor. These multiple processing elements are then programmed to perform a fixed task on arrays of data. Because the arrays of processing elements are already fixed, the programmer must program them in a specific configuration or feed data to them in a unified manner to perform the task required.

In the past year, a number of companies have introduced these products, although many have yet to emerge in smart cameras or frame grabbers (see “New processor introductions at a glance”). To rapidly enable design-ins, semiconductor vendors are working with their customers to develop algorithms targeting specific markets. While companies such as Picochip are targeting new wireless standards such as high-speed downlink packet access (HSDPA) and 802.16-2004 WiMAX, others such as Exilent, PACT XPP Technologies, and Mathstar are offering image-processing-specific functions to their customers.

For example, Exilent has demonstrated the use of its D-Fabrix in converting RGB images into the luminance/chrominance color space. For rapid development of image-processing applications, Aspex Semiconductor provides an image-processing library, callable as C functions. These include functions such as 1-D and 2-D filters and 2-D FFT/iFFT and 2-D wavelet transforms that use the thousands of processing elements in the company’s Linedancer processing elements operating in parallel. PACT XPP Technologies also offers a number of libraries designed to perform FFT, including the implementation of a 32-point discrete cosine transform and 16-tap finite impulse response.

“Higher-resolution cameras, some exceeding 2k × 2k pixels, are becoming commonplace in machine vision,” says Doug Pihl, CEO of MathStar. “The same cameras are also capable of faster image acquisition, sometimes exceeding 100 frames/s. To cope with this data stream, the Camera Link interface was defined with scalability from one camera at low frame rates up to four cameras with very high resolution and frame rates.

“To process data at these rates,” he says, “the MathStar field programmable object array (FPOA) can provide two to four times the performance of an FPGA while retaining the flexibility of a programmable device.” At present, the company has developed a number of application notes showing how the FPOA can be used for such functions as image scaling and FFT data analysis. Likely as not, the first customer for the device will be Alacron (Nashua, NH, USA; www.alacron.com), which has already announced the Fast-X frame grabber based on the device (see Vision Systems Design, November 2005, p. 97).


New processor introductions at a glance

Aspex Semiconductor (Sunnyvale, CA, USA; www.aspex-semi.com)
Linedancer integrates thousands of small processing elements, all operating in parallel. Multiple devices can be cascaded together in a one-dimensional string.

Elixent (Menlo Park, CA, USA; www.elixent.com)
D-Fabrix processing array uses 4-bit arithmetic logic units, registers, and a “switchbox,” which combines two of each into “tiles” that are combined to create the D-Fabrix array.

MathStar (Minneapolis, MN, USA; www.mathstar.com)
Field programmable object arrays are reprogrammable ICs that feature a number of arithmetic logic units, register files, and multiply-acculmulators that can be interconnected.

PACT XPP Technologies (Los Gatos, CA, USA; www.pactcorp.com)
An array of configurable processing elements is the heart of the XPP. The array is built from a number of different processing elements (PEs) that include ALU-PEs for basic computations, RAM-PEs for data, and I/O elements that connect internal elements to external RAMs or data ports.

Picochip (San Jose, CA, USA; www.picochip.com)
The PC102 chip consists of an array of RISC processors, co-processors, and peripherals. PC102 devices can be cascaded horizontally and vertically into a 2-D array to form signal-processing systems.

Quicksilver Technology (San Jose, CA, USA; www.qstech.com)
QuickSilver Technology’s Adapt2000 ACM System Platform enables ASIC, DSP, FPGA, and microprocessor technologies to be incorporated within a single IC, an adaptive computing machine (ACM).

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