• Sharc DSP introduces SIMD processing

    The ADSP-21160 next-generation Sharc digital signal processor uses 32-bit Super Harvard and single-instruction-multiple-data architectures to provide 600 MFLOPS peak and 400 MFLOPS sustained. It can also process 1 billion math operations/s on both floating-point and fixed-point data types. The DSP can execute a 1024-point, bit-reversed, complex FFT in 46 ms. Other features include a 100-MHz, 10-ns core instruction cycle, two computational processing elements, dual data address generators, 4 Mb
    July 1, 1998

    Sharc DSP introduces SIMD processing

    The ADSP-21160 next-generation Sharc digital signal processor uses 32-bit Super Harvard and single-instruction-multiple-data architectures to provide 600 MFLOPS peak and 400 MFLOPS sustained. It can also process 1 billion math operations/s on both floating-point and fixed-point data types. The DSP can execute a 1024-point, bit-reversed, complex FFT in 46 ms. Other features include a 100-MHz, 10-ns core instruction cycle, two computational processing elements, dual data address generators, 4 Mbits of SRAM, and 14 channels of zero-overhead DMA. The 2.5/3.3-V DSP comes in a 400-ball PBGA package and costs $300. Analog Devices Inc., Three Technology Way, Norwood, MA 02062; (800) 262-5643; Fax: (800) 446-6212.

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