Inspection speeds wafer production
Vision system simultaneously checks 2- and 3-D images of wafer bumps and flip-chip substrates.
As microelectronic circuits get smaller, they present increasing challenges to all test-and-measurement modalities. Now, bumped-wafer/flip-chip technology is shrinking even package-feature critical dimensions (CDs) to the Rayleigh resolution limit for visible-light inspection. To ensure reliable chip/package interconnections, no inspection modality is better than automated inspection, but the technique requires a combination of 2- and 3-D inspections that lead to complex test strategies involving long inspection sessions on multiple stations. Aceris 3D, an inspection-equipment developer, worked with camera-manufacturer Adimec Electronic Imaging to develop a multicamera inspection head that unites 2- and 3-D measurement systems and makes the technologies work simultaneously.