Providing multiple-processor support to DSP designs
Stephen J. Bradshaw
Having established the market for multiple-processor digital-signal processing (DSP) with the TMS320C4x series of processors, Texas Instruments (Dallas, TX) chose not to continue with the TMS320C4x Comport model or on-chip support for a multiple-processor capability in its TMS320C6000 series. Some may see the lack of support for multiple-processor DSP to be a disadvantage. However, by considering the applications that require multiple digital-signal processors, it is clear that mechanisms used for interconnecting processors can become the limiting factor when communications requirements become significant. Improvements are required. From this perspective, expectations of a DSP building block for multiple-processor DSP begin to change.
In vision-system applications, data bandwidths exceed those that can be supported across the conventional narrow-bandwidth (low tens of megabytes per second) point-to-point communication paths such as TMS320C4x communication ports or SHARC link ports. In multicast systems, which involve sending information from a single source, such as a high-speed camera, to multiple processors, such communication paths do not provide an efficient means of distributing the same information between processors and other I/O resources within the same system.
Alternatively, shared memory is an excellent mechanism for distributing information in this manner. However, there is the problem of sustaining the high data throughput required. What is needed is a suitable wide-bandwidth interprocessor communication infrastructure that can transfer information between the resources of the multiple-processor system in a manner that is consistent with the application.
TMS320C6000 digital-signal processors already have a wide-bandwidth interface called the memory bus. One option for connecting processors together could be to memory map the ends of high-speed FIFO devices between the memory busses of each of the processors. Commercially available FIFO devices are certainly capable of such bandwidths. This approach is seen in board-level designs, but will probably not be used for extensible systems where higher levels of connectivity are required because the number of FIFO chips required quickly becomes a limiting factor.
Also, the point-to-point approach does not support more complex capabilities such as data multicasting. To develop such capabilities, point-to-multipoint capabilities are required and are being designed by a number of multiple-processor digital-signal-processor companies.
To achieve this level of functionality, however, designers must completely abstract themselves from specific processor details, to the point where generic models can be established that are independent of processor type.The result is a next-generation multiple-processor architecture, capable of extending the capabilities of multiple-processor DSP systems in a manner more consistent with application requirements and that rely on nothing more than the DSP memory bus for integration into the multiple-processor environment. Details of this architecture and how it was derived can be obtained on the World Wide Web at www.traquair.com/technical.notes/ technology/pllarch.pdf.
STEPHEN J. BRADSHAW is president, Traquair Data Systems, Ithaca, NY 14850.
