JANUARY 28--Leveraging its strengths in data-converter design and low-voltage differential signaling (LVDS), National Semiconductor Corp. (Santa Clara, CA; www.national.com) has announced the capability to integrate serialized LVDS outputs into analog-to-digital (A/D) converters with an embedded clock. At very high speeds, the outputs of an A/D converter generate noise, resulting in lower dynamic performance and high system electromagnetic interference (EMI). The industry addressed this problem with parallel LVDS outputs with low voltage swings. National improved the solution by developing technology with serialized LVDS outputs, further improving dynamic performance and reducing system EMI.
"National proved this technology by integrating an LVDS serializer with a 10-bit, 40-MSPS A/D converter, which resulted in superior performance over all industry-leading 10-bit, 40-MSPS parallel products," said Robert Eddy, marketing director for National's Data Conversion Systems product group. "National will continue to strengthen its low power, CMOS, high performance, high-speed A/D portfolio by releasing products incorporating serialized LVDS outputs over the next two quarters. This technology enables National to deliver higher levels of integration which were prohibited in the past by pin count and a reduction in A/D converter performance due to noise."
An example of the impact of this technology is shown in medical imaging systems. In ultrasound systems using 128 A/D converter channels, the integrated LVDS output structure with an embedded clock eliminates 1024 traces on the board. This reduction in trace count provides a huge cost savings and facilitates a smaller form factor while greatly reducing EMI.
National's 10-bit, 40-MSPS A/D converter technology with parallel outputs (10 pins) updates the digital data at a rate of 40 MSPS. The same converter with serialized LVDS outputs with an embedded clock transforms the digital data into a single LVDS serial data (2-pin) stream with an embedded clock at a data rate of 400 MSPS. Since the clock is embedded in the data stream, clock-to-data skew is eliminated. This technology also offers a synchronization mode, which allows a deserializer to establish lock to a signal within specified lock times.
