Image signal processor IP designed for high contrast imaging

March 19, 2021
The IP runs exclusively in FPGAs, freeing up CPU and GPU resources.

The Denali 3.0 Programmable Image Signal Processor IP runs exclusively in FPGA fabric and provides a 20-bit pipeline, limiting latency to less than 20 lines according to the manufacturer, and with no external DRAM or frame buffers required.

It is based on proprietary HDR technology designed to enable retention of local image contrast and details in highlights and shadows without halos or color shifts. The IP can be adapted to support any resolution, non-traditional color filter arrays, and various HDR capture methods.  

The IP can support the complete line of Xilinx Zynq 7000 series and Zynq UltraScale+ programmable SoCs, offers native support for the ON Semiconductor AR0233.


To Learn More:

Contact: Pinnacle Imaging Systems
Headquarters: San Francisco, CA, USA
Product: Denali 3.0 Programmable Image Signal Processor IP
Key Features: Runs exclusively in FPGA fabric, 20-bit pipeline, limits latency to 20 lines.

What Pinnacle Imaging Systems says:
View more information on the Denali 3.0 Programmable Image Signal Processor IP.

Share your vision-related news by contacting Dennis Scimeca, Associate Editor, Vision Systems Design

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