Intellectual property cores target image processing

Designers of image-processing systems looking for ways to increase overall speed should consider the intellectual-property (IP) core offerings available in both field-programmable gate arrays (FPGAs) and VHDLs. Not only are functions such as video space encoding, conversion, discrete cosine transform (DCT), and JPEG available, but also the cores can be used as part of FPGA systems and custom ASIC-based designs.

Apr 1st, 2000

Designers of image-processing systems looking for ways to increase overall speed should consider the intellectual-property (IP) core offerings available in both field-programmable gate arrays (FPGAs) and VHDLs. Not only are functions such as video space encoding, conversion, discrete cosine transform (DCT), and JPEG available, but also the cores can be used as part of FPGA systems and custom ASIC-based designs.

Many FPGA manufacturers and their partners are now providing image-processing functions as IP cores. Through its AllianceCore program, for example, Xilinx (San Jose, CA) offers several parts, including the CVBS PAL/NTSC encoder from Sican Microelectronics (Palo Alto, CA), the RGB-to-YCrCb color space converter from Perigee (Liverpool, NY), and devices from Mentor Graphics (Wilsonville, OR) that include an 8 x 8 DCT processor.

"Digital imaging applications typically need the power of 32-bit processors for implementing the computationally intensive DCT and inverse DCT (IDCT) functions in software," says Robert Bielby, Xilinx director of strategic applications. "By moving the DCT/IDCT functions into an FPGA, designers can now use 8-bit microcontrollers and reduce overall system costs."

This month, Xentec (Oakville, Ontario, Canada) joins Sican, Perigee, and Mentor Graphics with two IP parts that target Xilinx Virtex-E and Spartan-II FPGAs. These cores include DCT and IDCT cores and a JPEG codec. Whereas the DCT/IDCT cores support Virtex, Virtex-E, and Spartan-II devices, the JPEG codec supports Virtex and Virtex-E devices.

"Xentec developed image-compression cores by using the DSP features in Spartan-II and Virtex architectures," says Mark Bowlby, manager of the Xilinx AllianceCORE program. "Although the DCT/IDCT cores enable hardware implementation of the forward and inverse DCT functions in a Spartan-II device, the JPEG codec provides an integrated encoder-decoder pair for image-compression and decompression applications," he notes.

Xentec's DCT/IDCT cores perform both DCT and IDCT functions and suit systems that require both image compression and decompression. They support DCT and IDCT on 8 x 8 image pixel data. The Xentec X/JPEG codec core conforms to the ISO/IEC 10918-1 JPEG baseline specification and performs both compression and decompression functions.

"The memory hierarchy in the Xilinx Virtex-E FPGAs enabled us to develop a small JPEG core," says Xerxes Wania, president and chief executive officer of Xentec. "Distributed SelectRAM was used to build ROM-based Huffman tables that are distributed across the design and embedded block SelectRAM for the large DCT/IDCT, quantization, and zigzag coding tables," he adds.

Xentec's DCT and IDCT cores are available in Spartan-II, Virtex-E, and Virtex FPGAs and list at $10,000 for the netlist versions. The JPEG codec is available for use in Virtex-E and Virtex FPGAs, and lists at $30,000.

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