Use the roadmap that works for you
Andy Wilson Editor at Large
As systems integrators, most of our readers buy and use OEM products to build their machine-vision and imaging systems. To affirm this relationship, OEM suppliers often discuss future product developments with their larger system-integration customers to ensure a smooth feature/performance upgrade path.
Under nondisclosure agreements, many systems integrators discover either planned or future product upgrades long before they are disclosed to the trade press or the OEM`s own sales force. What is more, many OEMs develop product "roadmaps" that detail future developments in terms of features, performance, and price. In addition to providing ideas of what future products may look like, such roadmaps are also used as marketing tools by OEM suppliers striving to ensure that their existing customer base remains in place. Over the years, these roadmaps have shown systems integrators smooth upgrade paths from EISA to the PCI bus, from VME to the CompactPCI bus, and from single-processor systems to heterogeneous, multiprocessor solutions.
Although OEM roadmaps are supposed to offer a feeling of product security, they might, however, do just the opposite. For example, with the introduction of its latest C67xx floating-point digital-signal processors (DSPs), Texas Instruments (TI; Dallas, TX) did not build on the architecture used in its extremely popular C40 product line (see Vision Systems Design, June 1998, p. 56). Instead, the company chose to develop a processing approach based around a very-long-instruction-word (VLIW) architecture to dramatically increase the performance of DSP algorithms.
Because the VLIW architecture used in TI`s C67xx departs radically from that used in the C40, the image-processing software developed for the C40 has to be recompiled before it can be run on the C67xx series. Fortunately, TI supplies a fine C compiler for the new architecture. But pity those system integrators who have tweaked assembly language code to optimize image- or signal-processing code for the C40. Porting optimized code from the C40 processor to the new C67xx is not an easy task.
Whereas TI`s roadmap for its C67xx leads to increased performance at the expense of a completely new architecture, the latest Sharc DSP (ADSP-21160) from Analog Devices (Norwood, MA) shows some consistency with the company`s earlier Harvard architecture designs. In this Sharc DSP, Analog Devices has chosen to replicate a multiply/accumulate stage in the processor`s Harvard architecture. By doing this, the company has developed a single-instruction multiple-data device that is code-compatible with its older Sharc devices. Of course, should system integrators opt to take advantage of the second processing stage in the new DSP, they too must repartition and recompile code. Rather than populate its roadmap with several different architectures, Analog Devices` roadmap presents a single unified architecture that can be expanded in terms of speed, remain compatible with older architectures, and should provide a familiar upgrade path.
Although this approach may be best for existing customers, those looking at new products that are not tied to existing architectures or legacy code will explore all available architectures to increase performance. In doing so, however, systems integrators should be wary of product roadmaps that could lead them to increased software-development costs and to systems that cannot be easily upgraded. System integrators may wish to focus on future compatibility, rather than the latest and fastest DSP.
